mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 325

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mcf51jf128

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mcf51jf128
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Mcf51jf128 Reference Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Chapter 14
Crossbar Switch
14.1 Introduction
This chapter provides information on the layout, configuration, and programming of the
crossbar switch. The crossbar switch connects bus masters and bus slaves using a
crossbar switch structure. This structure allows up to four bus masters to access different
bus slaves simultaneously, while providing arbitration among the bus masters when they
access the same slave.
14.1.1 Features
The crossbar switch includes these distinctive features:
14.2 Memory Map / Register Definition
This design was meant to be as small as possible. To help achieve this, the crossbar
switch contains no memory-mapped registers for configuring.
Freescale Semiconductor, Inc.
• Symmetric crossbar bus switch implementation
• 32-bit width and support for byte, 2-byte, 4-byte, and 16-byte burst transfers
• Operation at a 1-to-1 clock frequency with the bus masters
• Low-power park mode support
• Dynamic master priority elevation
• Allows concurrent accesses from different masters to different slaves
• Slave arbitration attributes configured on a slave by slave basis
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
325

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