mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 314

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map and Registers
13.2.20 Clock Divider 0 Register (SIM_CLKDIV0)
The following Reset row refers to Chip POR. Only that type of reset, or any reset type
that triggers Chip POR, affects this register. Other reset types do not affect this register.
Address: SIM_CLKDIV0 is FFFF_80C0h base + 1Bh offset = FFFF_80DBh
* Notes:
•
314
OUTDIV bitfield:At end of reset, loaded with either 0000 or 1111 depending on flash option register bit 0 (FOPT[0])
Reserved
OUTDIV
Field
Reset
Field
Read
7–4
3–0
Write
Bit
011
100
101
110
111
This read-only bitfield is reserved and always has the value zero.
Clock output divider value to generate CPU clock
Sets the divide value for the core/system clock.
NOTE: At the end of reset, this field is loaded with either 0000 or 1111 depending on flash option
Restriction: This bitfield cannot be changed when the MCU is in a VLPx mode.
Restriction: The CPU clock should never exceed 50 MHz.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
7
0
Division by 8
Division by 16
Division by 32
Division by 64
Division by 128 (reset value)
Divide-by-1
Divide-by-2
Divide-by-3
Divide-by-4
Divide-by-5
Divide-by-6
Divide-by-7
Divide-by-8
Divide-by-9
Divide-by-10
register bit 0 (FOPT[0]).
SIM_CLKOUT field descriptions (continued)
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
SIM_CLKDIV0 field descriptions
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Table continues on the next page...
0
5
Preliminary
0
4
Description
Description
3
*
2
*
OUTDIV
Freescale Semiconductor, Inc.
1
*
0
*