mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 288

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
The following pseudocode explains basic MAC or MSAC instruction functionality. This
example is presented as a case statement covering the three basic operating modes with
signed integers, unsigned integers, and signed fractionals. Throughout this example, a
comma-separated list in curly brackets, {}, indicates a concatenation operation.
switch (MACSR[6:5])
{
288
• Unless otherwise noted, the value of MACSR[N,Z] is based on the result of the final
• The overflow (V) flag is managed differently. It is set if the complete product cannot
• For the MAC design, the assembler syntax of the MAC (multiply and add to
• The optional 1-bit shift of the product is specified using the notation {<< | >>} SF,
case 0:
operation that involves the product and the accumulator.
be represented as a 40-bit value (this applies to 32 × 32 integer operations only) or if
the combination of the product with an accumulator cannot be represented in the
given number of bits. The EMAC design includes an additional product/
accumulation overflow bit for each accumulator that are treated as sticky indicators
and are used to calculate the V bit on each MAC or MSAC instruction. See MAC
Status Register (MACSR).
accumulator) and MSAC (multiply and subtract from accumulator) instructions does
not include a reference to the single accumulator. For the EMAC, assemblers support
this syntax and no explicit reference to an accumulator is interpreted as a reference to
ACC0. Assemblers also support syntaxes where the destination accumulator is
explicitly defined.
where <<1 indicates a left shift and >>1 indicates a right shift. The shift is performed
before the product is added to or subtracted from the accumulator. Without this
operator, the product is not shifted. If the EMAC is in fractional mode (MACSR[F/I]
is set), SF is ignored and no shift is performed. Because a product can overflow, the
following guidelines are implemented:
if (MACSR.OMC == 0 || MACSR.PAVn == 0)
• For unsigned word and longword operations, a zero is shifted into the product on
• For signed, word operations, the sign bit is shifted into the product on right shifts
• For all left shifts, a zero is inserted into the lsb position.
right shifts.
unless the product is zero. For signed, longword operations, the sign bit is shifted
into the product unless an overflow occurs or the product is zero, in which case a
zero is shifted in.
then {
/* MACSR[S/U, F/I] */
/* signed integers */
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Freescale Semiconductor, Inc.