mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1279

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

This figure shows PBMR. PBMR is accessible in supervisor mode using the WDEBUG
instruction and via the BDM port using the WRITE_DREG command. PBMR only
masks PBR0.
50.3.10 Address Breakpoint Registers (ABLR, ABHR)
The ABLR and ABHR define regions in the processor’s data address space that can be
used as part of the trigger. These register values are compared with the address for each
transfer on the processor’s high-speed local bus. The trigger definition register (TDR)
identifies the trigger as one of three cases:
Freescale Semiconductor, Inc.
DRc: 0x09
R
W
Reset
R
W
Reset
• Identical to the value in ABLR
Mask
31–1
Field
Field
V
0
31
–
15
–
Table 50-28. Program Counter Breakpoint Mask Register (PBMR)
30
–
14
–
Valid bit
This bit must be set for the PC breakpoint to occur at the address specified in the Address field.
0
1
PC breakpoint mask
If using PBR0, this register must be initialized since it is undefined after reset.
0
1
Description
Description
29
–
13
–
Table 50-27. PBRn Field Descriptions (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
28
–
12
–
Table 50-29. PBMR Field Descriptions
PBR is disabled.
PBR is enabled.
The corresponding PBR0 bit is compared to the appropriate PC bit.
The corresponding PBR0 bit is ignored.
27
–
11
–
26
–
10
–
25
–
9
–
Preliminary
24
–
8
–
Mask
Mask
23
–
7
–
22
–
6
–
21
–
5
–
20
–
4
–
Access: Supervisor write-only
19
3
–
–
18
–
2
–
Chapter 50 Debug
BDM write-only
17
–
1
–
16
–
0
–
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