mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1200

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mcf51jf128

Manufacturer Part Number
mcf51jf128
Description
Mcf51jf128 Reference Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Functional description
When a port pin is controlled by EGPIO, the port is configured for digital functionality,
so reading the the pin value (PV) register always returns the actual logic level on the
pads.
46.4.1.2 Operation when another on-chip module controls pin
When a pin is controlled by another on-chip module, the PTDD bit associated with the
pin does not affect the input or output direction of the pin. However, when the PTDD bit
is set, reading the port data (D) register still returns the last value written to the port data
register's associated bit. When the PTDD bit is cleared and the port pin is configured for
digital functionality, a read of the port data register still returns the actual logic level on
the pad.
46.4.1.3 Pin value register
For port pins that are configured as digital pins, no matter as input or output, pin value
register read always reflects logic level on pads. For port pins that are controlled by
analog functions, pin value register read returns zeros (off-value).
46.4.2 Port control
The following figure diagrams the PCTRL function.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
1200
Freescale Semiconductor, Inc.

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