mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 117

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

3.9.1.2 PDB Overview
Many applications need to synchronize the time that multiple ADC samples are taken
with respect to an external trigger or event. The programmable delay block provides
controllable delays from an external trigger or a programmable interval tick to the sample
trigger input of the ADCs and DACs.
3.9.1.3 PDB instantiation
The following table identifies PDB input trigger options.
Freescale Semiconductor, Inc.
Trigger 0
Trigger 1
Trigger 2
Trigger 3
Trigger 4
Trigger 5
Trigger 6
Trigger 7
Trigger 8
Trigger 9
Trigger 10
Trigger 11
Trigger 12
Trigger 13
Trigger 14
Trigger 15
PDB trigger
Number of triggers per ADC channel
Additional channel for PulseOut
Number of channels for ADC
Number of channels for DAC
Number of DAC triggers
PDB feature
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Table 3-38. PDB output channels
0b0000
0b0001
0b0010
0b0011
0b0100
0b0101
0b0110
0b0111
0b1000
0b1001
0b1010
0b1011
0b1100
0b1101
0b1110
0b1111
Trigger configuration
Preliminary
PDB_EXTRG
CMP Output
reserved
reserved
reserved
reserved
reserved
reserved
FTM0
FTM1
reserved
MTIM output
LPTMR0
reserved
LPTMR1
Software trigger
PDB input
Details
1
2
1
1
1
Chapter 3 Chip Configuration
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