mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1141

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor, Inc.
Reserved
Reserved
27–26
23–21
WSF
Field
BCE
SEF
FEF
FR
SR
28
25
24
20
19
18
Enables/disables transmitter operation in debug mode. The transmit bit clock is not affected by debug
mode.
0
1
Bit Clock Enable
Enables the transmit bit clock, separately from the transmit enable. This bit is automatically set whenever
the transmit enable is set. When software clears this bit, the transmit bit clock remains enabled (and this
bit remains set) until the end of the current frame.
0
1
This read-only bitfield is reserved and always has the value zero.
FIFO reset
Resets the FIFO pointers.
0
1
Software reset
When set, resets the internal transmitter logic including the FIFO pointers. Software visible-registers are
not affected, except for the status registers.
0
1
This read-only bitfield is reserved and always has the value zero.
Word start flag
Indicates that the start of the configured word has been detected. Write a logic one to this register bit to
clear this flag.
0
1
Sync error flag
Indicates that an error in the externally-generated frame sync has been detected. Write a logic one to this
register bit to clear this flag.
0
1
FIFO error flag
Indicates that an enabled transmit FIFO has underrun. Write a logic one to this register bit to clear this
flag.
Transmitter is disabled in debug mode, after completing the current frame.
Transmitter is enabled in debug mode.
Transmit bit clock is disabled
Transmit bit clock is enabled
No effect.
FIFO reset.
No effect.
Software reset.
Start of word not detected.
Start of word detected.
Sync error not detected.
Frame sync error detected.
I2Sx_TCSR field descriptions (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Chapter 44 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI)
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Preliminary
Description
1141