mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 256

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Processor Exceptions
11.3.3.10 RTE and Format Error Exception
The default operation of the V1 ColdFire processor is the generation of an illegal address
reset event if an RTE format error is detected. If CPUCR[ARD] is set, the reset is
disabled and a processor exception is generated as detailed below.
When an RTE instruction is executed, the processor first examines the 4-bit format field
to validate the frame type. For a ColdFire core, any attempted RTE execution (where the
format is not equal to {4,5,6,7}) generates a format error. The exception stack frame for
the format error is created without disturbing the original RTE frame and the stacked PC
pointing to the RTE instruction.
The selection of the format value provides some limited debug support for porting code
from M68000 applications. On M68000 family processors, the SR was located at the top
of the stack. On those processors, bit 30 of the longword addressed by the system stack
pointer is typically zero. Thus, if an RTE is attempted using this old format, it generates a
format error on a ColdFire processor.
If the format field defines a valid type, the processor: (1) reloads the SR operand, (2)
fetches the second longword operand, (3) adjusts the stack pointer by adding the format
value to the auto-incremented address after the fetch of the first longword, and then (4)
transfers control to the instruction address defined by the second longword operand
within the stack frame.
11.3.3.11 TRAP Instruction Exception
The TRAP #n instruction always forces an exception as part of its execution and is useful
for implementing system calls. The TRAP instruction may be used to change from user to
supervisor mode.
This set of 16 instructions provides a similar but expanded functionality compared to the
S08's SWI (software interrupt) instruction. Do not confuse these instructions and their
functionality with the software-scheduled interrupt requests, which are handled like
normal I/O interrupt requests by the interrupt controller. The processing of the software-
scheduled IRQs can be masked, based on the interrupt priority level defined by the SR[I]
field.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
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