mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 735

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

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33.3.5 Channel n Control Register 1 (PDBx_CHnC1)
Each PDB channel has one Control Register, CHnC1. The bits in this register control the
functionality of each PDB channel operation.
Addresses: PDB0_CH0C1 is FFFF_8540h base + 10h offset = FFFF_8550h
Freescale Semiconductor, Inc.
Bit
W
R
Reserved
31
0
31–24
23–16
15–0
IDLY
15–8
Field
Field
TOS
BB
30
0
29
0
28
0
0
PDB Interrupt Delay
These bits specify the delay value to schedule the PDB interrupt. It can be used to schedule an
independent interrupt at some point in the PDB cycle. If enabled, a PDB interrupt is generated, when the
counter is equal to the IDLY. Reading these bits returns the value of internal register that is effective for
the current cycle of the PDB.
This read-only bitfield is reserved and always has the value zero.
PDB Channel Pre-Trigger Back-to-Back Operation Enable
These bits enable the PDB ADC pre-trigger operation as back-to-back mode. Only lower M pre-trigger bits
are implemented in this MCU. Back-to-back operation enables the ADC conversions complete to trigger
the next PDB channel pre-trigger and trigger output, so that the ADC conversions can be triggered on
next set of configuration and results registers. Application code must only enable the back-to-back
operation of the PDB pre-triggers at the leading of the back-to-back connection chain.
0
1
PDB Channel Pre-Trigger Output Select
These bits select the PDB ADC pre-trigger outputs. Only lower M pre-trigger bits are implemented in this
MCU.
0
1
27
0
PDB channel's corresponding pre-trigger back-to-back operation disabled.
PDB channel's corresponding pre-trigger back-to-back operation enabled.
PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral
clock cycle after a rising edge is detected on selected trigger input source or software trigger is
selected and SWTRIG is written with 1.
PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register
plus one peripheral clock cycle after a rising edge is detected on selected trigger input source or
software trigger is selected and SETRIG is written with 1.
26
0
25
0
24
0
PDBx_IDLY field descriptions (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
23
0
22
0
PDBx_CHnC1 field descriptions
21
0
Table continues on the next page...
20
0
BB
19
0
18
0
Preliminary
17
0
16
0
15
0
Description
Description
14
0
13
0
12
0
Chapter 33 Programmable Delay Block (PDB)
TOS
11
0
10
0
0
9
0
8
0
7
0
6
0
5
4
0
EN
0
3
0
2
0
1
735
0
0