mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 551

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Reset
24.3.3 Chip select control register (FB_CSCRn)
Each CSCRn controls the auto-acknowledge, address setup and hold times, port size,
burst capability, and number of wait states.
Addresses: FB_CSCR0 is FFFF_E800h base + 8h offset = FFFF_E808h
Freescale Semiconductor, Inc.
Bit
W
R
Reserved
31
0
31–22
21–20
ASET
Field
Field
30
0
FB_CSCR1 is FFFF_E800h base + 14h offset = FFFF_E814h
29
0
28
0
The CSCR0 reset value differs from the other CSCRs:
See the Chip Configuration details for your particular device for
information on the exact CSCR0 reset value.
NOTE: At reset, no chip-select can be used until the CSMR0[V] is set. Afterward, FB_CS[1:0] functions
0
1
This read-only bitfield is reserved and always has the value zero.
Address setup
Controls the assertion of the chip-select with respect to assertion of a valid address and attributes. The
address and attributes are considered valid at the same time FB_TS/FB_ALE asserts.
00
01
27
0
• Bits 31-23 are 0
• Bit 22 is device-dependent
• Bits 21-10 are 1
• Bits 9-5 are device-dependent
• Bits 4-0 are 0
0
Chip select invalid
Chip select valid
26
0
Assert FB_CSn on first rising clock edge after address is asserted. (Default FB_CS1)
Assert FB_CSn on second rising clock edge after address is asserted.
25
0
as programmed.
24
0
FB_CSMRn field descriptions (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
23
0
22
0
FB_CSCRn field descriptions
21
0
Table continues on the next page...
20
0
19
0
18
0
Preliminary
NOTE
17
0
16
0
15
0
Description
Description
14
0
13
0
Chapter 24 External Bus Interface (Mini-FlexBus)
WS
12
0
11
0
10
0
0
9
0
8
0
7
PS
0
6
0
5
4
0
0
3
0
0
2
0
1
551
0
0