mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1113

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Chapter 43 Universal Asynchronous Receiver/Transmitter (UART)
43.4.2.9.1 Idle input line wakeup (C1[WAKE] = 0)
In this wakeup method, an idle condition on the unsynchronized receiver input signal
clears the C2[RWU] bit and wakes the UART. The initial frame or frames of every
message contain addressing information. All receivers evaluate the addressing
information, and receivers for which the message is addressed process the frames that
follow. Any receiver for which a message is not addressed can set its C2[RWU] bit and
return to the standby state. The C2[RWU] bit remains set and the receiver remains in
standby until another idle character appears on the unsynchronized receiver input signal.
Idle line wakeup requires that messages be separated by at least one idle character and
that no message contains idle characters.
When C2[RWU] is one and S2[RWUID] is zero, the idle character that wakes the
receiver does not set the S1[IDLE] flag or the receive data register full flag, S1[RDRF].
The receiver wakes and waits for the first data character of the next message which will
be stored in the receive data buffer. When S2[RWUID] and C2[RWU] bits are set and
C1[WAKE] is cleared, any idle condition sets the S1[IDLE] flag and generates an
interrupt if enabled.
Idle Input Line Wakeup is not supported when C7816[ISO_7816E] is set/enabled.
43.4.2.9.2 Address mark wakeup (C1[WAKE] = 1)
In this wakeup method, a logic 1 in the bit position immediately preceding the stop bit of
a frame clears the C2[RWU] bit and wakes the UART. A logic 1 in the bit position
immediately preceeding the stop bit marks a frame as an address frame that contains
addressing information. All receivers evaluate the addressing information, and the
receivers for which the message is addressed process the frames that follow. Any receiver
for which a message is not addressed can set its C2[RWU] bit and return to the standby
state. The C2[RWU] bit remains set and the receiver remains in standby until another
address frame appears on the unsynchronized receiver input signal.
A logic 1 in the bit position immediately preceding the stop bit clears the receiver's
C2[RWU] bit before the stop bit is received and places the received data into the receiver
data buffer.
Address mark wakeup allows messages to contain idle characters but requires that the bit
position immediately preceding the stop bit be reserved for use in address frames.
If module is in standby mode and nothing triggers to wake the UART, no error flag is set
even if an invalid error condition is detected on the receiving data line.
Address mark wakeup is not supported when C7816[ISO_7816E] is set/enabled.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Freescale Semiconductor, Inc.
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