mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 429

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

19.4.3 Dual-Address Data Transfer Mode
Each channel supports dual-address transfers. Dual-address transfers consist of a source
data read and a destination data write. The DMA controller module begins a dual-address
transfer sequence after a DMA request. If no error condition exists, DSRn[REQ] is set.
If a termination error occurs, DSRn[BES, DONE] are set and DMA transactions stop.
19.4.4 Advanced Data Transfer Controls: Auto-Alignment
This section describes auto-alignment for DMA transfers. Typically, this DMA feature is
applicable for transfers of large blocks of data, and therefore is not applicable for
peripheral-initiated cycle-steal transfers.
Auto-alignment allows block transfers to occur at the optimal size based on the address,
byte count, and programmed size. To use this feature, DCRn[AA] must be set. The
source is auto-aligned if DCRn[SSIZE] indicates a transfer size larger than
DCRn[DSIZE]. Source alignment takes precedence over the destination when the source
and destination sizes are equal. Otherwise, the destination is auto-aligned. The address
register chosen for alignment increments regardless of the increment value. Configuration
error checking is performed on registers not chosen for alignment.
If BCRn is greater than 16, the address determines transfer size. Bytes, words, or
longwords are transferred until the address is aligned to the programmed size boundary,
at which time accesses begin using the programmed size.
Freescale Semiconductor, Inc.
• Dual-address read—The DMA controller drives the SARn value onto the system
• Dual-address write—The DMA controller drives the DARn value onto the system
address bus. If DCRn[SINC] is set, the SARn increments by the appropriate number
of bytes upon a successful read cycle. When the appropriate number of read cycles
complete (multiple reads if the destination size is larger than the source), the DMA
initiates the write portion of the transfer.
address bus. When the appropriate number of write cycles complete (multiple writes
if the source size is larger than the destination), DARn increments by the appropriate
number of bytes if DCRn[DINC] is set. BCRn decrements by the appropriate number
of bytes. DSRn[DONE] is set when BCRn reaches zero. If the BCRn is greater than
zero, another read/write transfer is initiated if continuous mode is enabled
(DCRn[CS] = 0).
If a termination error occurs, DSRn[BED, DONE] are set and DMA transactions
stop.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Chapter 19 DMA Controller
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