mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 943

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

38.5.1 Initialization Sequence
Before the SPI module can be used for communication, an initialization procedure must
be carried out, as follows:
38.5.2 Pseudo-Code Example
In this example, the SPI module will be set up for master mode with only hardware match
interrupts enabled. The SPI will run in 16-bit mode at a maximum baud rate of bus clock
divided by 2. Clock phase and polarity will be set for an active-high SPI clock where the
first edge on SPSCK occurs at the start of the first cycle of a data transfer.
Freescale Semiconductor, Inc.
SPIx_C1=0x54(%01010100)
1. Update control register 1 (SPIx_C1) to enable the SPI and to control interrupt
2. Update control register 2 (SPIx_C2) to enable additional SPI functions such as the
3. Update the baud rate register (SPIx_BR) to set the prescaler and bit rate divisor for
4. Update the hardware match register ( SPIx_MH:SPIx_ML) with the value to be
5. In the master, read SPIx_S while SPTEF = 1, and then write to the transmit data
enables. This register also sets the SPI as master or slave, determines clock phase and
polarity, and configures the main SPI options.
SPI match interrupt feature, the master mode-fault function, and bidirectional mode
output. 8- or 16-bit mode select and other optional features are controlled here as
well.
an SPI master.
compared to the receive data register for triggering an interrupt if hardware match
interrupts are enabled.
register ( SPIx_DH:SPIx_DL) to begin transfer.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
MCF51JF128 Reference Manual, Rev. 2, 03/2011
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Preliminary
0
1
0
1
0
1
0
0
Disables receive and mode fault interrupts
Enables the SPI system
Disables SPI transmit interrupts
Sets the SPI module as a master SPI device
Configures SPI clock as active-high
First edge on SPSCK at start of first data transfer cycle
Determines SS pin function when mode fault enabled
SPI serial data transfers start with most significant bit
Chapter 38 Serial Peripheral Interface (SPI)
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