mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1318

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
PST value is generated. Returning to the example with compression enabled, the
execution of ten sequential instructions generates a single PST value indicating ten
sequential instructions have been executed.
This technique has proven to be effective at significantly reducing the average PST
entries per instruction and PST entries per machine cycle. The application of this
compression technique makes the application of a useful PST trace buffer for the V1
ColdFire core realizable. The resulting 5-bit PST definitions are shown in the following
table.
1318
PST[4:0]
0x0C–
0x08–
0x0B
0x0F
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
Continue execution. Many instructions execute in one processor cycle. If an instruction requires more processor
clock cycles, subsequent clock cycles are indicated by driving PST with this encoding.
Begin execution of one instruction. For most instructions, this encoding signals the first processor clock cycle of
an instruction's execution. Certain change-of-flow opcodes, plus the PULSE and WDDATA instructions,
generate different encodings.
Reserved
Entry into user-mode. Signaled after execution of the instruction that caused the ColdFire processor to enter
user mode.
Begin execution of PULSE and WDDATA instructions. PULSE defines triggers or markers for debug and/or
performance analysis. WDDATA lets the core write any operand (byte, word, or longword) directly to the DDATA
port, independent of debug module configuration. When WDDATA is executed, a value of 0x04 is signaled on
the PST port, followed by the appropriate marker, and then the data transfer on the DDATA port. The number of
captured data bytes depends on the WDDATA operand size.
Begin execution of taken branch or SYNC_PC BDM command. For some opcodes, a branch target address
may be displayed on DDATA depending on the CSR settings. CSR also controls the number of address bytes
displayed, indicated by the PST marker value preceding the DDATA nibble that begins the data output. This
encoding also indicates that the SYNC_PC command has been processed.
Reserved
Begin execution of return from exception (RTE) instruction.
Indicates the number of data bytes to be loaded into the PST trace buffer. The capturing of peripheral bus data
references is controlled by CSR[DDC].
0x08 Begin 1-byte data transfer on DDATA
0x09 Begin 2-byte data transfer on DDATA
0x0A Reserved
0x0B Begin 4-byte data transfer on DDATA
Indicates the number of address bytes to be loaded into the PST trace buffer. The capturing of branch target
addresses is controlled by CSR[BTB].
0x0C Reserved
0x0D Begin 2-byte address transfer on DDATA (Displayed address is shifted right 1: ADDR[16:1])
0x0E Begin 3-byte address transfer on DDATA (Displayed address is shifted right 1: ADDR[23:1])
0x0F Reserved
Definition
Table 50-41. CF1 Debug Processor Status Encodings
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Table continues on the next page...
Preliminary
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