mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1156

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Reset
Memory Map and Registers
44.3.15 SAI Receive Configuration 5 Register (I2Sx_RCR5)
This register cannot be altered when the receive enable bit is set.
Addresses: I2S0_RCR5 is FFFF_8200h base + 94h offset = FFFF_8294h
1156
Bit
W
R
Reserved
Reserved
Reserved
31
0
31–29
28–24
WNW
Field
FSD
Field
FSE
FSP
7–5
MF
30
4
3
2
1
0
0
0
29
0
28
0
This read-only bitfield is reserved and always has the value zero.
MSB first
Specifies whether the LSB or the MSB is transmitted/received first.
0
1
Frame sync early
0
1
This read-only bit is reserved and always has the value zero.
Frame sync polarity
Configures the polarity of the frame sync.
0
1
Frame sync direction
Configures the direction of the frame sync.
0
1
This read-only bitfield is reserved and always has the value zero.
Word N width
27
0
WNW
LBS is transmitted/received first.
MBS is transmitted/received first.
Frame sync asserts with the first bit of the frame.
Frame sync asserts one bit before the first bit of the frame.
Frame sync is active high.
Frame sync is active low.
Frame Sync is generated externally (slave mode).
Frame Sync is generated internally (master mode).
26
0
25
0
24
0
I2Sx_RCR4 field descriptions (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
23
0
22
0
0
I2Sx_RCR5 field descriptions
21
0
Table continues on the next page...
20
0
19
0
W0W
18
0
Preliminary
17
0
16
0
15
0
Description
Description
14
0
0
13
0
12
0
11
0
FBT
10
0
0
9
0
8
Freescale Semiconductor, Inc.
0
7
0
6
0
5
4
0
0
0
3
0
2
0
1
0
0