mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 149

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

The LPBOOT bit provides the flexibility to select a lower frequency, low power boot
option. The flash erased state defaults to fast clocking mode, because where the low
power boot (LPBOOT) bit resides in flash is logic 1 in the flash erased state.
To enable the low power boot option, program LPBOOT (in the option byte of the FTFL
module's flash configuration field) to 0. During the reset sequence, if LPBOOT is 0, the
system is in a slow clock configuration. Upon any system reset, the clock dividers return
to this configurable reset state.
5.2.5 Clock gating
The clock to each module can be individually gated on and off using the SIM's SCGCx
registers. These bits are cleared after any reset, which disables the clock to the
corresponding module to conserve power. Prior to initializing a module, set the
corresponding bit in SCGCx register to enable the clock. Before turning off the clock,
disable the module or place the module in its default configuration.
Turning off the clock for an enabled, working module can produce unexpected behavior.
Any bus access to a peripheral that has its clock disabled generates a bus error.
5.2.6 Module clocks
The following table summarizes the clocks associated with each module.
Freescale Semiconductor, Inc.
CPU
CAU
RNG
DBG
BDM
EzPort
DMA
RAM
BUSCLK
Module
CPUCLK
SYSCLK
BUSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Bus interface clock
Table 5-4. Module clock options
Table continues on the next page...
Core and system peripherals
External memory interface
Flash (and FlexMemory)
Preliminary
CPUCLK
MCGBDCCLK
Internal clocks
EZP_CLK
Chapter 5 Clock Distribution
I/O interface clocks
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