mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 775

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

36.4.3 Background Debug Mode Operation
When the microcontroller is in active background debug mode, the CMT temporarily
suspends all counting until the microcontroller returns to normal user mode.
36.5 CMT External Signal Descriptions
This table shows the description of the external signal.
36.5.1 CMT_IRO — Infrared Output
This output signal is driven by the modulator output when MSC[MCGEN] is set and
OC[IROPEN] is set. The CMT_IRO signal starts a valid transmission with a delay, after
MSC[MCGEN] bit be asserted to high, that can be calculated based on two register bits.
The following table shows how to calculate this delay.
If MSC[MCGEN] bit is cleared and OC[IROPEN] bit is set, the signal is driven by
OC[IROL] bit. This enables user software to directly control the state of the CMT_IRO
signal by writing to OC[IROL] bit. If OC[IROPEN] bit is cleared, the signal is disabled
and is not driven by the CMT module. Therefore, CMT can be configured as a modulo
timer for generating periodic interrupts without causing signal activity.
36.6 Memory Map/Register Definition
The following registers control and monitor CMT operation.
The address of a register is the sum of a base address and an address offset. The base
address is defined at the chip level. The address offset is defined at the module level.
Freescale Semiconductor, Inc.
CMT_IRO
Signal
MSC[CMTDIV] = 0
MSC[CMTDIV] > 0
Infrared Output
Description
Condition
Table 36-3. CMT_IRO signal delay calculation
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Table 36-2. CMT Signal Descriptions
Preliminary
Chapter 36 Carrier Modulator Transmitter (CMT)
Delay (bus clock cycles)
(PPS{PPSDIV] × 2) + 3
PPS[PPSDIV] + 2
I/O
O
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