mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1194

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map and Registers
46.3.7 Port Interrupt Pin Enable Register (PCTLx_IPE)
This register's bits enable control of pin interrupts.
Addresses: PCTLA_IPE is FFFF_9200h base + 6h offset = FFFF_9206h
1194
PTDMAEN
PTIPE[7:0]
Reserved
PTMOD
PTIE
Field
Reset
Field
6–2
Read
7–0
Write
7
1
0
Bit
PCTLB_IPE is FFFF_9210h base + 6h offset = FFFF_9216h
PCTLC_IPE is FFFF_9220h base + 6h offset = FFFF_9226h
PCTLD_IPE is FFFF_9230h base + 6h offset = FFFF_9236h
PCTLE_IPE is FFFF_9240h base + 6h offset = FFFF_9246h
PCTLF_IPE is FFFF_9250h base + 6h offset = FFFF_9256h
DMA enable
Determines whether the pin DMA request is enabled. If it is enabled, the pin DMA request is asserted
when an interrupt flag of any pin is set (at least one bit of the IF register is set). Meanwhile, a synchronous
interrupt from the IF register is disabled if this bit is set.
0
1
This read-only bitfield is reserved and always has the value zero.
Interrupt enable
Determines whether a pin interrupt is requested to the CPU.
0
1
Direction mode for pin interrupt
This bit (along with the EDG bits) controls the detection mode of the pin interrupt for pins.
0
1
Interrupt pin enables
Each PTIPE bit enables the corresponding pin for a pin interrupt.
7
0
Pin DMA request is disabled and synchronous interrupt from IF is allowed.
Pin DMA request is enabled and synchronous interrupt from IF is disabled.
Pin interrupt request not enabled.
Pin interrupt request enabled.
Pin interrupt detects edges only.
Pin interrupt detects both edges and levels.
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
PCTLx_IPE field descriptions
PCTLx_IC field descriptions
0
5
Preliminary
0
4
PTIPE[7:0]
Description
Description
0
3
0
2
Freescale Semiconductor, Inc.
0
1
0
0