mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 299

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

13.2.5 System Options Register 5 (SIM_SOPT5)
Address: SIM_SOPT5 is FFFF_80C0h base + 4h offset = FFFF_80C4h
Freescale Semiconductor, Inc.
VLLDBGREQ
Reserved
Reserved
Reserved
STOPE
WAITE
MECS
Field
Reset
Field
7–6
3–1
Read
7–4
3–2
Write
5
4
0
Bit
This read-only bitfield is reserved and always has the value zero.
Stop mode enable
This bit can be written only once after each reset.
0
1
Wait mode enable
0
1
This read-only bitfield is reserved and always has the value zero.
Very Low Leakage Debug Request upon Wakeup
This bit can be written through the BDM interface.
0
1
This read-only bitfield is reserved and always has the value zero.
MTIM16 external clock source select
00
01
10
11
7
0
Disable entry to stop mode
Enable entry to stop mode
Disable entry to wait mode
Enable entry to wait mode
Wakeup from a VLLSx mode (except via the RESET pin) is via Chip POR into single chip mode (reset
value)
Wakeup from a VLLSx mode (except via the RESET pin) is via Chip POR into active background
debug mode
TMR_CLKIN0 (reset value)
TMR_CLKIN1
FTM0 Ch1 Out
FTM1Ch1 Out
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
0
SIM_SOPT4 field descriptions
SIM_SOPT5 field descriptions
Table continues on the next page...
0
5
Preliminary
0
4
Description
Description
0
3
Chapter 13 System Integration Module (SIM)
MECS
0
2
F1ECS
1
1
F0ECS
0
0
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