mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 762

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory map and register definition
35.3.1 Low Power Timer Control Status Register (LPTMRx_CSR)
Addresses: LPTMR0_CSR is FFFF_84C0h base + 0h offset = FFFF_84C0h
762
Reset
Reset
FFFF_84DC Low Power Timer Counter Register (LPTMR1_CNR)
FFFF_84D8 Low Power Timer Compare Register (LPTMR1_CMR)
Absolute
address
Bit
Bit
W
W
Reserved
(hex)
R
R
31–8
Field
TCF
TIE
7
6
31
15
0
0
LPTMR1_CSR is FFFF_84D0h base + 0h offset = FFFF_84D0h
30
14
0
0
This read-only bitfield is reserved and always has the value zero.
Timer Compare Flag
The timer compare flag is set when the LPTMR is enabled and the LPTMR Counter Register equals the
LPTMR Compare Register and increments. This Timer Compare Flag is cleared when the LPTMR is
disabled or a logic one is written to the Timer Compare Flag.
0
1
Timer Interrupt Enable
When the Timer Interrupt Enable is set, the LPTMR Interrupt is generated whenever the Timer Compare
Flag is also set.
0
1
LPTMR Counter Register has not equaled the LPTMR Compare Register and incremented
LPTMR Counter Register has equaled the LPTMR Compare Register and incremented
Timer Interrupt Disabled.
Timer Interrupt Enabled.
29
13
0
0
28
12
0
0
MCF51JF128 Reference Manual, Rev. 2, 03/2011
0
Register name
LPTMRx memory map (continued)
27
11
0
0
LPTMRx_CSR field descriptions
Table continues on the next page...
26
10
0
0
25
0
0
9
Preliminary
24
0
0
8
0
Description
TCF
w1c
23
0
0
7
TIE
22
0
0
6
(in bits)
Width
32
32
21
0
0
5
TPS
Access
R/W
R
20
0
0
4
Freescale Semiconductor, Inc.
TPP
Reset value
0000_0000h
0000_0000h
19
0
0
3
TFC
18
0
0
2
17
0
0
1
Section/
35.3.3/
35.3.4/
page
765
766
TEN
16
0
0
0