mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 813

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

37.3.9 Channel Value High (FTMx_CnVH)
These registers contain the captured FTM counter value of the input capture function or
the match value for the output modes.
In input capture, capture test and dual edge capture modes, reading a single byte in CnV
latches the contents into a buffer where they remain latched until the other byte is read.
This latching mechanism also resets (becomes unlatched) when the CnSC register is
written (whether BDM mode is active or not). Any write to the channel registers is
ignored during these input modes.
When BDM is active, the read coherency mechanism is frozen such that the buffer
latches remain in the state they were in when the BDM became active, even if one or both
bytes of the channel value register are read while BDM is active. This assures that if you
were in the middle of reading a 16-bit register when BDM became active, it reads the
appropriate value from the other half of the 16-bit value after returning to normal
execution. Any read of the CnV registers in BDM mode bypasses the buffer latches and
returns the value of these registers and not the value of their read buffer.
In output modes, writing to CnV latches the value into a buffer. The registers are updated
with the value of their write buffer according to
Buffers.
If MODE[FTMEN] = 0, this write coherency mechanism may be manually reset by
writing to the CnSC register (whether BDM mode is active or not). This latching
mechanism allows coherent 16-bit writes in either big-endian or little-endian order which
is friendly to various compiler implementations.
Freescale Semiconductor, Inc.
Reserved
ELSA
DMA
Field
2
1
0
ELSB is write protected. It can be written only when MODE[WPDIS] = 1.
Edge or Level Select
The functionality of ELSB and ELSA depends on the channel mode. See the table in the register
description.
ELSA is write protected. It can be written only when MODE[WPDIS] = 1.
This read-only bit is reserved and always has the value zero.
DMA Enable
Enables DMA transfers for the channel.
0
1
Disable DMA transfers.
Enable DMA transfers.
FTMx_CnSC field descriptions (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Description
Update of the Registers With Write
Chapter 37 FlexTimer (FTM)
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