mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 412

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Introduction
Read Data Bus
The terms peripheral request and DREQ refer to a DMA request from one of the on-chip
peripherals or package pins. The DMA provides hardware handshake signals: either a
DMA acknowledge (DACK) or a done indicator back to the peripheral. For details on the
connections associated with DMA request inputs, see the register definition for DMA
Request Control (DMAREQC).
19.1.2 Features
The DMA controller module features:
412
• Four independently programmable DMA controller channels
Peripheral Bus
SysBus Interface
Slave
Data Path
Write Data Bus
Requests
Channel
Figure 19-1. 4-Channel DMA Block Diagram
DREQ0
MCF51JF128 Reference Manual, Rev. 2, 03/2011
16
Channel 0
DCR0
SAR0
DAR0
DSR0
BCR0
DACK0
Data Path
Control
16
Channel
Enables
DREQ1
16
Channel 1
Control
DAR1
DSR1
BCR1
DCR1
SAR1
MUX
DACK1
Preliminary
16
Arbitraton/
Control
MUX
DREQ2
Attributes
Channel 2
16
Channel
DAR2
DSR2
BCR2
DCR2
SAR2
DACK2
16
System Bus Address
System Bus Size
Current Master Attributes
DREQ3
Channel 3
16
DAR3
DSR3
BCR3
DCR3
SAR3
DACK3
16
SysBus Interface
Freescale Semiconductor, Inc.
Interrupts
Addr + Attr
Phase Bus Signals
Registered Addr