mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1036

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map and Registers
42.3.10 I2C Address Register 2 (I2Cx_A2)
Addresses: I2C0_A2 is FFFF_81C0h base + 9h offset = FFFF_81C9h
1036
Reserved
SHTF2IE
SHTF2
Field
Reset
Field
SAD
Read
7–1
Write
1
0
0
Bit
I2C1_A2 is FFFF_81D0h base + 9h offset = FFFF_81D9h
I2C2_A2 is FFFF_81E0h base + 9h offset = FFFF_81E9h
I2C3_A2 is FFFF_81F0h base + 9h offset = FFFF_81F9h
0
1
SCL high timeout flag 2
This bit sets when SCL is held high and SDA is held low more than clock × LoValue/512. Software clears
this bit by writing a 1 to it.
0
1
SHTF2 interrupt enable
Enables SCL high and SDA low timeout interrupt.
0
1
SMBus address
Contains the slave address used by the SMBus. This field is used on the device default address or other
related addresses.
This read-only bit is reserved and always has the value zero.
7
1
No SCL high and SDA high timeout occurs
SCL high and SDA high timeout occurs
No SCL high and SDA low TIMEOUT occurs
SCL high and SDA low TIMEOUT occurs
Disabled
Enabled
I2Cx_SMB field descriptions (continued)
1
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
I2Cx_A2 field descriptions
0
5
Preliminary
SAD
0
4
Description
Description
0
3
0
2
Freescale Semiconductor, Inc.
1
1
0
0
0