mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1266

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map and Register Descriptions
1266
APCDIV16
PSTBWA
PSTBST
D1HRL
PSTBR
22–21
19–16
15–8
Field
20
7
6
5
PST Trace Buffer State
Indicates the current state of PST trace buffer recording.
00
01
10
11
Reserved. Must write 0.
Debug 1-pin Hardware Revision Level
Indicates the hardware revision level of the 1-pin debug module implemented in the core. For this
device, this field is 3h.
PST Trace Buffer Write Address
Indicates the current write address of the PST trace buffer. The most significant bit of this field is
sticky; if set, it remains set until a PST/DDATA reset event occurs. As the core inserts PST and
DDATA packets into the trace buffer, this field is incremented. The value of the write address
defines the next location in the PST trace buffer to be loaded. In other words, the contents of
PSTB[PSTBWA – 1] is the last valid entry in the trace buffer.
The most-significant bit of this field can be used to determine if the entire PST trace buffer has been
loaded with valid data.
The PSTBWA is unaffected when a buffer stop condition has been reached, the buffer is disabled,
or a system reset occurs. This allows the contents of the PST trace buffer to be retrieved after
these events to assist in debug.
NOTE: Because this device contains a 64-entry trace buffer, PSTBWA[6] is always zero.
Bit 7
0
1
PST Trace Buffer Reset
Generates a reset of the PST trace buffer logic, which clears PSTBWA and PSTBST. The same
resources are reset when a disabled trace buffer becomes enabled and upon the receipt of a BDM
GO command when operating in obtrusive trace mode. These reset events also clear any
accumulation of PSTs. This bit always reads as 0b.
0
1
Automatic PC Synchronization Divide Cycle Counts by 16
Divides the cycle counts for automatic SYNC_PC command insertion by 16. See the
XCSR[APCSC] and XCSR[APCENB] fields.
Reserved. Must write 0.
Description
Table 50-12. CSR2 Field Descriptions (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Disabled
Enabled and waiting for the start condition
Enabled, recording, and waiting for the stop condition
Enabled, completed recording after the stop condition was reached
PSTB valid data locations (oldest to newest)
0, 1, ..., PSTBWA – 1
PSTBWA, PSTBWA + 1, ..., 0, 1, ..., PSTBWA – 1
No reset
Force a PST trace buffer reset
Table continues on the next page...
Preliminary
Freescale Semiconductor, Inc.