mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 626

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional description
28.3 Functional description
28.3.1 CRC initialization/re-initialization
To enable the CRC calculation, the user must program the SEED, POLYNOMIAL, and
necessary parameters for transpose and CRC result inversion in the applicable registers.
Asserting the CTRL[WAS] bit enables the programming of the SEED value into the CRC
data register.
After a completed CRC calculation, re-asserting the CTRL[WAS] bit and programming a
seed (whether the value is new or a previously used seed value) re-initialize the CRC
module for a new CRC computation. All other parameters must be set before
programming the seed value and subsequent data values.
28.3.2 CRC calculations
In 16-bit and 32-bit CRC modes, data values can be programmed 8 bits, 16 bits, or 32 bits
at a time, provided all bytes are contiguous. Non-contiguous bytes can lead to an
incorrect CRC computation.
28.3.2.1 16-bit CRC
Compute a 16-bit CRC with the following steps:
626
1. Clear the CTRL[TCRC] bit to enable 16-bit CRC mode.
2. Program the transpose and complement options in the CTRL register as required for
Reserved
the CRC calculation. See
TCRC
Field
7–0
8
0
1
Width of CRC protocol.
0
1
This read-only bitfield is reserved and always has the value zero.
Writes to the CRC data register are data values.
Writes to the CRC data register are seed values.
16-bit CRC protocol.
32-bit CRC protocol.
CRC_CTRL field descriptions (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Transpose feature
Preliminary
Description
and
CRC result complement
Freescale Semiconductor, Inc.
for details.