mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1307

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

50.4.1.5.18 WRITE_CREG
If the processor is halted, this command writes the 32-bit operand to the selected control
register. This register grouping includes the PC, SR, CPUCR, MACSR, MASK, ACC,
VBR, and OTHER_A7. Accesses to processor control registers are always 32-bits wide,
regardless of implemented register width. The register is addressed through the core
register number (CRN). See
If the processor is not halted, this command is rejected as an illegal operation and no
operation is performed.
50.4.1.5.19 WRITE_DREG
This command writes the 32-bit operand to the selected debug control register. This
grouping includes all the debug control registers ({X}CSRn, BAAR, AATR, TDR,
PBRn, PBMR, ABxR, DBR, DBMR). Accesses to debug control registers are always 32-
bits wide, regardless of implemented register width. The register is addressed through the
core register number (CRN).
Freescale Semiconductor, Inc.
When writing XCSR, CSR2, or CSR3, WRITE_DREG only
writes bits 23–0. The upper byte of these debug registers is only
written with the special WRITE_XCSR_BYTE,
WRITE_CSR2_BYTE, and WRITE_CSR3_BYTE commands.
Write debug control register
Write CPU control register
0xC0+CRN
0x80+CRN
host
host
target
target
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Table 50-39
CREG data
DREG data
[31-24]
host
host
[31-24]
target
target
Preliminary
CREG data
DREG data
for the CRN details when CRG is 11.
host
host
[23-16]
[23-16]
Note
target
target
CREG data
DREG data
host
host
[15-8]
target
[15-8]
target
Active Background
DREG data
CREG data
host
host
target
target
Non-intrusive
[7-0]
[7-0]
D
Y
D
Y
L
L
Chapter 50 Debug
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