mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 794

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

CMT Interrupts and DMA
If MSC[EOCIE] bit is high when MSC[EOCF] bit is set, the CMT module will generate
an interrupt request or a DMA transfer request.
MSC[EOCF] bit must be cleared to prevent from being generated another event (interrupt
or DMA request) after exiting the service routine. See following table.
The EOC interrupt is coincident with loading the down-counter with the contents of
CMD1:CMD2 and loading the space period register with the contents of CMD3:CMD4.
The EOC interrupt provides a means for the user to reload new mark/space values into
the modulator data registers. Modulator data register updates will take effect at the end of
the current modulation cycle. Note that the down-counter and space period register are
updated at the end of every modulation cycle, irrespective of interrupt handling and the
state of the EOCF flag.
794
DMA[DM
A]
0
1
MSC[EOCIE]
X
X
Table 36-19. How to clear MSC[EOCF] bit
MCF51JF128 Reference Manual, Rev. 2, 03/2011
MSC[EOCF] bit is cleared by reading the CMT modulator status and control register
MSC followed by an access of CMD2 or CMD4.
MSC[EOCF] bit is cleared by the CMT DMA transfer done.
Description
Preliminary
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