mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 87

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

1. In the format x(y): x is the interrupt level and y is the priority within the level.
2. Upon exiting LLS mode, core instruction execution goes directly to the low leakage wakeup interrupt. For wakeup from
3. All of the UART0 interrupt sources are joined in this single vector.
4. All of the UART1 interrupt sources are joined in this single vector.
Freescale Semiconductor, Inc.
0x188
0x18C
0x190
0x194
0x198
0x19C
0x1A0
0x1A4
0x1A8
0x1AC
0x1B0
0x1B4
0x1B8
0x1BC
0x1C0
0x1C4
0x1C8
0x1CC-0x3FC
Highest
Priority
VLLSx modes:
• One or two pending interrupts are serviced. One is serviced if the wakeup is from the LLWU wakeup pins, or two are
• Then instruction execution resumes via the reset vectors.
Address offset
Table 3-11. ColdFire Level, Priority within Level Matrix Interrupt Assignments
serviced if the wakeup is from a TSI, CMP, or LPTMR module.
7
Level
Table 3-10. Exception vector assignments (continued)
7
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115-255
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Vector number
6
Table continues on the next page...
5
Preliminary
2(3)
2(2)
2(1)
1(7)
1(6)
7(0)
6(0)
5(0)
4(0)
3(0)
2(0)
1(0)
1(5)
1(4)
1(3)
1(2)
1(1)
-
Level (Priority)
4
Priority within Level
IRQ
Midpoint
1
LVD
DAC
CMT
PDB
LPTMR0
LPTMR1
Level 7 Software Interrupt
Level 6 Software Interrupt
Level 5 Software Interrupt
Level 4 Software Interrupt
Level 3 Software Interrupt
Level 2 Software Interrupt
Level 1 Software Interrupt
MTIM
USBDCD
EGPIO PORT A | EGPIO PORT B
EGPIO PORT D | EGPIO PORT C
EGPIO PORT F | EGPIO PORT E
RESERVED - Unused for ColdFire core
devices
1
3
Low
Leakage
Wakeup
Chapter 3 Chip Configuration
2
Assignment
MCG
Loss of
Clock
1
Level 7
SWI
0
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