mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1078

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Module Memory Map
43.3.12 UART Control Register 5 (UARTx_C5)
Addresses: UART0_C5 is FFFF_8140h base + Bh offset = FFFF_814Bh
1078
Reserved
Reserved
TDMAS
RDMAS
Reset
Field
Read
4–0
Write
7
6
5
Bit
UART1_C5 is FFFF_8160h base + Bh offset = FFFF_816Bh
TDMAS
Transmitter DMA Select
TDMAS configures the transmit data register empty flag, S1[TDRE], to generate interrupt or DMA
requests if C2[TIE] is set.
NOTE: If C2[TIE] is cleared, TDRE DMA and TDRE interrupt request signals are not asserted when the
NOTE: If C2[TIE] and TDMAS are both set, then C2[TCIE] must be cleared, and D register must not be
0
1
This read-only bit is reserved and always has the value zero.
Receiver Full DMA Select
RDMAS configures the receiver data register full flag, S1[RDRF], to generate interrupt or DMA requests if
C2[RIE] is set.
NOTE: If C2[RIE] is cleared, the RDRF DMA and RDFR interrupt request signals are not asserted when
0
1
This read-only bitfield is reserved and always has the value zero.
7
0
If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request
interrupt service.
If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a
DMA transfer.
If C2[RIE] is set and the S1[RDRF] flag is set, the RDFR interrupt request signal is asserted to
request interrupt service.
If C2[RIE] is set and the S1[RDRF] flag is set, the RDRF DMA request signal is asserted to request a
DMA transfer.
TDRE flag is set, regardless of the state of TDMAS.
written outside of servicing of a DMA request.
the S1[RDRF] flag is set, regardless of the state of RDMAS.
0
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
UARTx_C5 field descriptions
RDMAS
0
5
Preliminary
0
4
Description
0
3
0
0
2
Freescale Semiconductor, Inc.
0
1
0
0