mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 438

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map/Register Definition
20.3.3 MCG Control 3 Register (MCG_C3)
Address: MCG_C3 is FFFF_8400h base + 2h offset = FFFF_8402h
* Notes:
•
1. A value for SCTRIM is loaded during reset from a factory programmed location .
438
x = Undefined at reset.
SCTRIM
IRCS
Field
Reset
Field
Read
7–0
Write
0
Bit
Controls whether the FLL (or PLL) is disabled in BLPI and BLPE modes. In FBE or PBE modes, setting
this bit to 1 will transition the MCG into BLPE mode; in FBI mode, setting this bit to 1 will transition the
MCG into BLPI mode. In any other MCG mode, LP bit has no affect.
0
1
Internal Reference Clock Select
Selects between the fast or slow internal reference clock source.
0
1
Slow Internal Reference Clock Trim Setting
SCTRIM
clock period. The SCTRIM bits are binary weighted (that is, bit 1 adjusts twice as much as bit 0).
Increasing the binary value increases the period, and decreasing the value decreases the period.
An additional fine trim bit is available in C4 register as the SCFTRIM bit. Upon reset this value is loaded
with a factory trim value.
If an SCTRIM value stored in nonvolatile memory is to be used, it is your responsibility to copy that value
from the nonvolatile memory location to this register.
x*
7
FLL (or PLL) is not disabled in bypass modes.
FLL (or PLL) is disabled in bypass modes (lower power) unless BDM is active.
Slow internal reference clock selected.
Fast internal reference clock selected.
1
controls the slow internal reference clock frequency by controlling the slow internal reference
x*
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
MCG_C2 field descriptions (continued)
MCG_C3 field descriptions
x*
5
Preliminary
x*
4
SCTRIM
Description
Description
x*
3
x*
2
Freescale Semiconductor, Inc.
x*
1
x*
0