mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 351

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

15.4.10 INTC Software IACK Register (INTC_SWIACK)
Refer to the description of the Level-n IACK registers.
Address: INTC_SWIACK is FFFF_FFC0h base + 20h offset = FFFF_FFE0h
Freescale Semiconductor, Inc.
Reserved
Reserved
VECN
Field
CLR
Reset
Field
7–6
5–0
Read
6–0
Write
7
Bit
This bitfield is reserved.
For data values within the 56–62 range, the corresponding bit in the INTC_FRC register is cleared, as
defined below.
NOTE: Data values outside this range do not affect the INTC_FRC register. It is recommended the data
111000
111001
111010
111011
111100
111101
111110
This read-only bit is reserved and always has the value zero.
Vector number
Indicates the appropriate vector number.
It is the highest-level, highest-priority request currently being asserted in the CF1_INTC module. If there
are no pending requests, VECN is zero.
7
0
0
values be restricted to the 0x38–0x3E (56–62) range to ensure compatibility with future devices.
Bit 56, INTC_FRC[LVL7] is cleared
Bit 57, INTC_FRC[LVL6] is cleared
Bit 58, INTC_FRC[LVL5] is cleared
Bit 59, INTC_FRC[LVL4] is cleared
Bit 60, INTC_FRC[LVL3] is cleared
Bit 61, INTC_FRC[LVL2] is cleared
Bit 62, INTC_FRC[LVL1] is cleared
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
INTC_SWIACK field descriptions
INTC_CFRC field descriptions
0
5
Preliminary
0
4
Description
Description
VECN
0
3
Chapter 15 Interrupt Controller (INTC)
0
2
0
1
0
0
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