mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1167

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Chapter 44 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI)
The FIFO data ready flag can generate an interrupt or a DMA request.
44.4.7.2 FIFO warning flag
The FIFO warning flag is set based on the number of entries in the FIFO.
The transmit warning flag is set when the number of entries in any of the enabled
transmit FIFOs is empty and is cleared when the number of entries in each enabled
transmit FIFO is not empty.
The receive warning flag is set when the number of entries in any of the enabled receive
FIFOs is full and is cleared when the number of entries in each enabled receive FIFO is
not full.
The FIFO warning flag can generate an Interrupt or a DMA request.
44.4.7.3 FIFO error flag
The transmit FIFO error flag is set when the any of the enabled transmit FIFOs
underflow. After it is set, all enabled transmit channels repeat the last valid word read
from the transmit FIFO until the transmit FIFO error flag is cleared and the start of the
next transmit frame. All enabled transmit FIFOs should be reset and initialized with new
data before the transmit FIFO error flag is cleared.
The receive FIFO error flag is set when the any of the enabled receive FIFOs overflow.
After it is set, all enabled receive channels discard received data until the receive FIFO
error flag is cleared and the start of the next receive frame. All enabled receive FIFOs
should be emptied before the receive FIFO error flag is cleared.
The FIFO error flag can generate an interrupt only.
44.4.7.4 Sync error flag
The sync error flag is set when configured for an externally generated frame sync and the
external frame sync asserts when the transmitter or receiver is busy with the previous
frame. The external frame sync assertion is ignored and the sync error flag is set. The
transmitter or receiver continues checking for frame sync assertion at the end of each
frame (or when idle) when the sync error flag is set.
The sync error flag can generate an interrupt only.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Freescale Semiconductor, Inc.
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