HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet
HD6417706F133
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HD6417706F133 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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SH7706 Group 32 Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/SH7700 Series The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are they are used ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Main Revisions for This Edition The list of revisions is a summary of points that ...
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... Bit order: Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx. Signal notation: Preface Product Code HD6417706F133 HD6417706BP133V The following notation is used for cases when the same or a similar function, e.g. serial communication, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel ...
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Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/eng/ SH7706 manuals: Document Title SH7706 Hardware Manual SH-3/SH-3E/SH3-DSP Programming Manual Users manuals ...
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Abbreviations ACIA Asynchronous Communication Interface Adapter ADC Analog to Digital Converter AUD Advanced User Debugger BSC Bus State Controller CPG Clock Pulse Generator CMT Compare Match Timer DAC Digital to Analog Converter DMA Direct Memory Access DMAC Direct Memory Access ...
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Rev. 5.00 May 29, 2006 page viii of xlviii ...
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Main Revisions for This Edition Item Page 1.3 Pin Assignment 4 Figure 1.2 Pin Assignment (FP-176C) 1.4 Pin Function 10 3.4.4 Avoiding 69 Synonym Problems Figure 3.9 Synonym Problem Revision (See Manual for Details) Figure amended MD3 167 MD4 168 ...
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Item Page 6.3.2 IRQ Interrupt 116 6.4.4 Interrupt 129 Request Register 0 (IRR0) Rev. 5.00 May 29, 2006 page x of xlviii Revision (See Manual for Details) Description amended When using edge-sensing for IRQ interrupts, clear the interrupt source by ...
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Item Page 6.4.4 Interrupt 130 Request Register 0 (IRR0) 8.1 Feature 163 8.4.4 Wait State 182 Control Register 2 (WCR2) Table 8.6 Area 6 Wait 184 Control (Normal Memory I/F) Table 8.7 Area 5 Wait 184 Control (Normal Memory I/F) ...
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Item Page 8.4.6 PCMCIA 192 Control Register (PCR) Table 8.10 Area 6 Wait Control (PCMCIA I/F) 8.5.4 Synchronous 222 DRAM Interface Figure 8.24 Auto- 229 Refresh Operation Rev. 5.00 May 29, 2006 page xii of xlviii Revision (See Manual for ...
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Item Page 8.5.4 Synchronous 233 DRAM Interface Figure 8.27 Synchronous DRAM Mode Write Timing 9.3.2 DMA 255 Destination Address Registers (DAR_0 to DAR_3) Revision (See Manual for Details) Figure amended and note added TRp1 TRp2 TRp3 TRp4 ...
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Item Page 9.5.2 Register 294 Description Compare Match Timer Control/Status Register (CMCSR) 9.5.3 Operation 295 Period Count Operation CMCNT Count Timing 296 Figure 9.28 Count Timing Rev. 5.00 May 29, 2006 page xiv of xlviii Revision (See Manual for Details) ...
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Item Page 9.6.1 Example of 299 DMA Transfer between A/D Converter and External Memory (Address Reload on) Table 9.7 Values in the DMAC after the Fourth Transfer Ends 9.7 Cautions 301, 302 Section 10 Clock 303 to Pulse Generator 305, ...
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Item Page 10.3 Clock Operating 308, Modes 309 Table 10.3 Available Combination of Clock Mode and FRQCR Values 10.3 Clock Operating 309 Modes Cautions: 10.6 Usage Note 313 When Using a PLL Oscillator Circuit: 13.3.15 RTC Control 352 Register 1 ...
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Item Page 14.3.8 SC Port 381 Control Register (SCPCR) 16.1 Feature 442 Figure 16.1 SCIF Block Diagram 16.3.6 Serial Control 451 Register 2 (SCSCR2) 16.4.1 Serial 479 Operation Serial data reception: Revision (See Manual for Details) Table amended Bit Bit ...
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Item Page Section 17 Pin 487 Function Controller (PFC) Table 17.1 List of Multiplexed Pins 17.1.6 Port F Control 498 Register (PFCR) 17.1.10 SC Port 503 Control Register (SCPCR) 18.6 Port F 517 Figure 18.6 Port F 18.10.2 SC Port ...
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Item Page Section 22 Power- 568 Down Modes Table 22.1 Power- Down Modes 22.3.3 Module 576 Standby Function Transition to Module Standby Function 24.3.1 Clock Timing 615 Figure 24.4 Power- On Oscillation Settling Time Revision (See Manual for Details) Table ...
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Item Page 24.3.6 Synchronous 646 DRAM Timing Figure 24.39 Synchronous DRAM Mode Register Write Cycle 24.3.7 PCMCIA 652 Timing Figure 24.45 PCMCIA I/O Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait) 24.3.12 Delay Time 663 Variation ...
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Item Page B.1 Pin Functions 669 Table B.1 Pin States during Resets, Power- Down States, and Bus- Released State 671 672 B.3 Processing of 677 Unused Pins Revision (See Manual for Details) Table amended and note 12 added Power-On Category ...
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... Figure D.1 Package Dimensions (FP-176C/ PLQP0176KD-A) Figure D.2 Package 694 Dimensions (TBP-208A/ TTBG0208JA-A) Rev. 5.00 May 29, 2006 page xxii of xlviii Revision (See Manual for Details) Table amended Model Marking Package HD6417706F133 176-pin plastic LQFP (FP-176C/PLQP0176KD-A) HD6417706BP133 208-pin TFBGA (TBP-208A/TTBG0208JA-A) Figure replaced Figure replaced ...
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Section 1 Overview ............................................................................................................. 1.1 Feature .............................................................................................................................. 1.2 Block Diagram .................................................................................................................. 1.3 Pin Assignment ................................................................................................................. 1.4 Pin Function ...................................................................................................................... Section 2 CPU ...................................................................................................................... 13 2.1 Register Description.......................................................................................................... 13 2.1.1 Privileged Mode and Banks ................................................................................. 13 2.1.2 General Registers ................................................................................................. 15 ...
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TLB Address Comparison ................................................................................... 63 3.3.4 Page Management Information............................................................................ 65 3.4 MMU Functions................................................................................................................ 66 3.4.1 MMU Hardware Management ............................................................................. 66 3.4.2 MMU Software Management .............................................................................. 66 3.4.3 MMU Instruction (LDTLB)................................................................................. 67 3.4.4 Avoiding Synonym Problems .............................................................................. 68 3.5 MMU ...
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General Exceptions .............................................................................................. 92 4.4.3 Interrupts.............................................................................................................. 95 4.5 Usage Note........................................................................................................................ 97 Section 5 Cache .................................................................................................................... 99 5.1 Feature .............................................................................................................................. 99 5.1.1 Cache Structure.................................................................................................... 99 5.2 Register Description.......................................................................................................... 101 5.2.1 Cache Control Register (CCR) ............................................................................ 101 5.2.2 Cache Control Register ...
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Interrupt Response Time................................................................................................... 135 Section 7 User Break Controller 7.1 Feature .............................................................................................................................. 139 7.2 Register Description.......................................................................................................... 141 7.2.1 Break Address Register A (BARA) ..................................................................... 141 7.2.2 Break Address Mask Register A (BAMRA)........................................................ 142 7.2.3 Break Bus Cycle Register A ...
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Synchronous DRAM Mode Register (SDMR) .................................................... 193 8.4.8 Refresh Timer Control/Status Register (RTCSR) ................................................ 193 8.4.9 Refresh Timer Counter (RTCNT)........................................................................ 196 8.4.10 Refresh Time Constant Register (RTCOR) ......................................................... 196 8.4.11 Refresh Count Register (RFCR) .......................................................................... 197 8.5 Operation .......................................................................................................................... ...
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Example of DMA Transfer between External Memory and SCIF Transmitter (Indirect Address on) ........................................................................................... 299 9.7 Cautions ............................................................................................................................ 301 Section 10 Clock Pulse Generator (CPG) 10.1 Feature .............................................................................................................................. 303 10.2 Input/Output Pin................................................................................................................ 306 10.3 Clock Operating Modes .................................................................................................... 306 ...
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Status Flag Set Timing......................................................................................... 337 12.5.2 Status Flag Clear Timing ..................................................................................... 337 12.5.3 Interrupt Sources and Priorities............................................................................ 338 12.6 Usage Note........................................................................................................................ 338 12.6.1 Writing to Registers ............................................................................................. 338 12.6.2 Reading Registers ................................................................................................ 338 Section 13 Realtime Clock (RTC) 13.1 ...
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Register Description.......................................................................................................... 367 14.3.1 Receive Shift Register (SCRSR).......................................................................... 368 14.3.2 Receive Data Register (SCRDR) ......................................................................... 368 14.3.3 Transmit Shift Register (SCTSR) ........................................................................ 368 14.3.4 Transmit Data Register (SCTDR)........................................................................ 368 14.3.5 Serial Mode Register (SCSMR)........................................................................... 369 14.3.6 Serial Control Register ...
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Serial Mode Register 2 (SCSMR2)...................................................................... 447 16.3.6 Serial Control Register 2 (SCSCR2).................................................................... 449 16.3.7 Serial Status Register 2 (SCSSR2)....................................................................... 452 16.3.8 Bit Rate Register 2 (SCBRR2)............................................................................. 460 16.3.9 FIFO Control Register 2 (SCFCR2) .................................................................... 466 16.3.10 FIFO Data Count ...
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Port E Data Register (PEDR)............................................................................... 516 18.6 Port F................................................................................................................................. 517 18.6.1 Register Description............................................................................................. 517 18.6.2 Port F Data Register (PFDR) ............................................................................... 518 18.7 Port G................................................................................................................................ 519 18.7.1 Register Description............................................................................................. 519 18.7.2 Port G Data Register (PGDR) .............................................................................. 520 18.8 ...
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Section 20 D/A Converter (DAC) 20.1 Feature .............................................................................................................................. 549 20.2 Input/Output Pin................................................................................................................ 550 20.3 Register Description.......................................................................................................... 550 20.3.1 D/A Data Registers 0 and 1 (DADR0 and DADR1)............................................ 550 20.3.2 D/A Control Register (DACR) ............................................................................ 550 20.4 Operation .......................................................................................................................... 552 Section ...
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Section 23 List of Registers 23.1 Register Address Map ....................................................................................................... 585 23.2 Register Bits...................................................................................................................... 591 23.3 Register States in Processing Mode .................................................................................. 602 Section 24 Electrical Characteristics 24.1 Absolute Maximum Ratings ............................................................................................. 607 24.2 DC Characteristics ............................................................................................................ 609 24.3 AC ...
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Section 1 Overview Figure 1.1 SH7706 Block Diagram....................................................................................... Figure 1.2 Pin Assignment (FP-176C) .................................................................................. Figure 1.3 Pin Assignment (TBP-208A) ............................................................................... Section 2 CPU Figure 2.1 Register Configuration......................................................................................... 14 Figure 2.2 General Registers ................................................................................................. 15 Figure 2.3 System Registers.................................................................................................. 16 Figure ...
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Section 6 Interrupt Controller (INTC) Figure 6.1 INTC Block Diagram........................................................................................... 114 Figure 6.2 Example of IRL Interrupt Connection ................................................................. 117 Figure 6.3 Interrupt Operation Flowchart ............................................................................. 134 Figure 6.4 Example of Pipeline Operations when IRL Interrupt Is Accepted....................... 138 Section ...
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Figure 8.31 Example of PCMCIA Interface............................................................................ 238 Figure 8.32 Basic Timing for PCMCIA Memory Card Interface ........................................... 239 Figure 8.33 Wait Timing for PCMCIA Memory Card Interface............................................. 240 Figure 8.34 Basic Timing for PCMCIA Memory Card Interface Burst Access...................... 241 ...
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Figure 9.17 Cycle-Steal Mode, Level Input (CPU Access: 2 Cycles)..................................... 286 Figure 9.18 Cycle-Steal Mode, Level Input (CPU Access: 3 Cycles)..................................... 286 Figure 9.19 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DMA RD Access: 4 Cycles) ......................................... 286 Figure ...
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Figure 13.3 Reading the Time................................................................................................. 358 Figure 13.4 Using the Alarm Function.................................................................................... 359 Figure 13.5 Example of Crystal Oscillator Circuit Connection .............................................. 360 Figure 13.6 Using Periodic Interrupt Function........................................................................ 361 Section 14 Serial Communication Interface (SCI) Figure 14.1 SCI Block ...
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Figure 15.10 Retransmission in SCI Transmit Mode ................................................................ 440 Section 16 Serial Communication Interface with FIFO (SCIF) Figure 16.1 SCIF Block Diagram............................................................................................ 442 Figure 16.2 SCPT[3]/SCK2 Pin .............................................................................................. 443 Figure 16.3 SCPT[2]/TxD2 Pin............................................................................................... 444 Figure 16.4 SCPT[2]/RxD2 Pin .............................................................................................. 444 ...
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Figure 19.8 A/D Conversion Timing ...................................................................................... 544 Figure 19.9 External Trigger Input Timing............................................................................. 545 Figure 19.10 Definitions of A/D Conversion Accuracy............................................................ 546 Figure 19.11 Example of Analog Input Protection Circuit ....................................................... 547 Figure 19.12 Analog Input Pin Equivalent Circuit.................................................................... 547 ...
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Figure 24.9 PLL Synchronization Settling Time at the Returning from Standby Mode (Return by IRQ/IRL Interrupt)............................................................................. 617 Figure 24.10 PLL Synchronization Settling Time when Frequency Multiplication Rate Modified ...................................................................................................... 618 Figure 24.11 Reset Input Timing .............................................................................................. 620 Figure 24.12 Interrupt ...
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Figure 24.37 Synchronous DRAM Auto-Refresh Timing (TRAS = 1, TPC = 1) ..................... 645 Figure 24.38 Synchronous DRAM Self-Refresh Cycle (TPC Figure 24.39 Synchronous DRAM Mode Register Write Cycle ............................................... 646 Figure 24.40 PCMCIA Memory Bus Cycle (TED = 0, ...
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Section 2 CPU Table 2.1 Initial Register Values ............................................................................................ 15 Table 2.2 Addressing Modes and Effective Addresses .......................................................... 23 Table 2.3 Instruction Formats ................................................................................................ 27 Table 2.4 Classification of Instructions.................................................................................. 30 Table 2.5 Data Transfer Instructions ...................................................................................... 34 Table 2.6 ...
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Table 6.7 Interrupt Response Time ........................................................................................ 136 Section 7 User Break Controller Table 7.1 Data Access Cycle Addresses and Operand Size Comparison Conditions ............ 154 Section 8 Bus State Controller (BSC) Table 8.1 Pin Configuration ................................................................................................... 165 Table 8.2 Physical ...
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Table 10.3 Available Combination of Clock Mode and FRQCR Values................................. 308 Section 12 Timer Unit (TMU) Table 12.1 Pin Configuration ................................................................................................... 325 Table 12.2 TMU Interrupt Sources .......................................................................................... 338 Section 13 Realtime Clock (RTC) Table 13.1 RTC Pin Configuration .......................................................................................... ...
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Table 16.4 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode)............................................................................................ 465 Table 16.5 Maximum Bit Rates during External Clock Input (Asynchronous Mode) ............. 465 Table 16.6 SCSMR2 Settings and SCIF Communication Formats .......................................... 469 Table 16.7 ...
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Table 22.3 Register States in Software Standby Mode ............................................................ 574 Section 24 Electrical Characteristics Table 24.1 Absolute Maximum Ratings................................................................................... 607 Table 24.2 DC Characteristics.................................................................................................. 609 Table 24.3 Permitted Output Current Values ........................................................................... 611 Table 24.4 Operating Frequency Range................................................................................... 612 Table ...
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The SH7706 is a RISC microprocessor that integrates a Renesas Technology-original RISC-type SuperH™ architecture SH-3 CPU as its core that has peripheral functions required for system configuration. The CPU of this LSI has upper compatibility with the SH-1 and SH-2 ...
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Section 1 Overview 32-bit internal data bus Logical address space: 4 Gbytes Space identifier ASID: 8 bits, 256 logical address space Abundant Peripheral Functions Memory Management Unit (MMU) User Break Controller (UBC) Bus state Controller (BSC) Direct Memory Access Controller ...
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Block Diagram MMU TLB CCN CACHE BRIDGE H-UDI INTC CPG/WDT External bus interface Legend: ADC : A/D converter AUD : Advanced user debugger BSC : Bus state controller CACHE : Cache memory CCN : Cache memory controller CMT : ...
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Section 1 Overview 1.3 Pin Assignment STATUS0/PTE[4] 133 STATUS1/PTE[5] 134 TCLK/PTE[6] 135 IRQOUT/PTE[7] 136 V Q 137 SS CKIO 138 V Q 139 CC TxD0/SCPT[0] 140 SCK0/SCPT[1] 141 TxD2/SCPT[2] 142 SCK2/SCPT[3] 143 RTS2/SCPT[4] 144 RxD0/SCPT[0] 145 RxD2/SCPT[2] 146 CTS2/IRQ5/SCPT[5] 147 ...
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Note: Section in the dotted lines are perspective view. Figure 1.3 Pin Assignment ...
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Section 1 Overview 1.4 Pin Function Number of Pins FP-176C TBP-208A Pin Name -RTC * XTAL2 3 C1 EXTAL2 -RTC * D31/PTB[ D30/PTB[ D29/PTB[5] ...
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Number of Pins FP-176C TBP-208A Pin Name 30 M2 D12 31 M3 D11 32 M4 D10 ...
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Section 1 Overview Number of Pins FP-176C TBP-208A Pin Name 60 U6 A13 A14 A15 65 P8 A16 66 R8 A17 67 T8 A18 68 U8 ...
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Number of Pins FP-176C TBP-208A Pin Name 84 R13 CS0 85 P13 86 U14 CS2/PTC[3] 87 T14 CS3/PTC[4] 88 R14 CS4/PTC[5] 89 U17 CS5/CE1A/PTC[6] 90 T17 CS6/CE1B/PTC[7] 91 R15 CE2A/PTD[6] 92 R16 93 R17 ...
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Section 1 Overview Number of Pins FP-176C TBP-208A Pin Name 107 L16 DRAK0/PTE[2] 108 L17 DRAK1/PTE[3] 109 K15 AUDATA[0]/PTF[0] 110 K16 AUDATA[1]/PTF[1] 111 K17 AUDATA[2]/PTF[2] 112 J14 AUDATA[3]/PTF[3] AUDSYNC/PTF[4] 113 J16 114 J17 TDI/PTG[0] 115 J15 V SS 116 H17 ...
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Number of Pins FP-176C TBP-208A Pin Name 133 A17 STATUS0/PTE[4] 134 A16 STATUS1/PTE[5] 135 C15 TCLK/PTE[6] IRQOUT/PTE[7] 136 B15 137 A15 138 C14 CKIO 139 B14 140 A14 TxD0/SCPT[0] 141 D13 SCK0/SCPT[1] 142 C13 ...
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Section 1 Overview Number of Pins FP-176C TBP-208A Pin Name 157 B9 NMI 158 159 C9 AUDCK/PTG[4] DREQ0/PTH[5] 160 A8 DREQ1/PTH[6] 161 B8 ADTRG/PTG[5] 162 C8 163 D8 MD0 164 B7 MD2 RESETP 165 A6 166 ...
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Register Description 2.1.1 Privileged Mode and Banks Processor Modes: There are two processor modes: user mode and privileged mode. The SH7706 normally operates in user mode, and enters privileged mode when an exception occurs or an interrupt is accepted. ...
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Section 2 CPU Switching between user mode and privileged mode is controlled by the processor mode bit (MD) in the status register. 31 R0_BANK0 * * 1 2 R1_BANK0 * 2 R2_BANK0 * 2 R3_BANK0 * 2 R4_BANK0 * 2 ...
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Register values after a reset are shown in table 2.1. Table 2.1 Initial Register Values Type General registers Control registers System registers Note: * Initial value is set at power-on-reset or manual-reset. 2.1.2 General Registers There are 16 general registers, ...
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Section 2 CPU 2.1.3 System Registers System registers can be accessed by the LDS and STS instructions. When an exception occurs, the contents of the program counter (PC) are saved in the saved program counter (SPC). The SPC contents are ...
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Control Registers Control registers can be accessed in privileged mode using the LDC and STC instructions. The GBR register can also be accessed in user mode. There are five control registers, as follows: Status register (SR) Saved status register ...
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Section 2 CPU Status Register (SR) The information of system status are set in this register. Bit Bit Name Initial Value All ...
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Bit Bit Name Initial Value 11, 10 All All Note: The and T ...
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Section 2 CPU Global Base Register (GBR) Stores base address of GBR-indirect addressing mode. The GBR-indirect addressing mode is used for on-chip supporting module register area data transfers and logic operations. The GBR register can also be accessed in user ...
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The data format in memory is shown in figure 2.5. Address Address Address A Byte0 Byte1 Address Word0 Address Big-endian mode 2.3 Instruction Features 2.3.1 Execution Environment Data ...
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Section 2 CPU T bit: The T bit in the status register (SR) is used to indicate the result of compare operations, and is read as a TRUE/FALSE condition determining if a conditional branch is taken or not. To improve ...
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Addressing Modes Addressing modes and effective address calculation methods are shown in table 2.2. Table 2.2 Addressing Modes and Effective Addresses Addressing Instruction Mode Format Effective Address Calculation Method Register Rn Effective address is register Rn. (Operand direct is ...
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Section 2 CPU Addressing Instruction Mode Format Effective Address Calculation Method Register @(disp:4, Effective address is register Rn contents indirect with Rn) with 4-bit displacement disp added. displacement After disp is zero-extended multiplied by 1 (byte), 2 (word), ...
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Addressing Instruction Mode Format Effective Address Calculation Method PC-relative @(disp:8, Effective address is register PC contents with PC) with 8-bit displacement disp added. displacement After disp is zero-extended multiplied by 2 (word (longword), according to the ...
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Section 2 CPU Addressing Instruction Mode Format Effective Address Calculation Method PC-relative Rn Effective address is sum of register PC and Rn contents. Immediate #imm:8 8-bit immediate data imm of TST, AND, OR, or XOR instruction is zero-extended. #imm:8 8-bit ...
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Instruction Formats Table 2.3 explains the meaning of instruction formats and source and destination operands. The meaning of the operands depends on the operation code. The following symbols are used. xxxx: Operation code mmmm: Source register nnnn: Destination register ...
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Section 2 CPU Instruction Format nm 15 format xxxx nnnn mmmm md 15 format xxxx xxxx mmmm nd4 15 format xxxx xxxx nnnn Rev. 5.00 May 29, 2006 page 28 of 698 REJ09B0146-0500 Source Destination Operand Operand 0 mmmm: register ...
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Instruction Format nmd 15 format xxxx nnnn mmmm d format 15 xxxx xxxx dddd d12 15 format xxxx dddd dddd nd8 15 format xxxx nnnn dddd i format 15 xxxx xxxx format 15 xxxx nnnn ...
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Section 2 CPU 2.4 Instruction Set 2.4.1 Instruction Set Classified by Function The SH7706 instruction set includes 68 basic instruction types, as listed in table 2.4. Table 2.4 Classification of Instructions Operation Classification Types Code Data transfer 5 MOV MOVA ...
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Operation Classification Types Code Arithmetic 21 MUL operations MULS MULU NEG NEGC SUB SUBC SUBV Logic 6 AND operations NOT OR TAS TST XOR Shift 12 ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLLn SHLR SHLRn SHAD SHLD Function Double-precision ...
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Section 2 CPU Operation Classification Types Code Branch BRA BRAF BSR BSRF JMP JSR RTS System 15 CLRMAC control CLRT CLRS LDC LDS LDTLB NOP PREF RTE SETS SETT SLEEP STC STS TRAPA Total: 68 The instruction ...
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Item Format Instruction OP.Sz SRC,DEST mnemonic Instruction MSB LSB code Operation , summary (xx) M/Q/T & <<n, >>n Privileged mode Execution cycles T bit Note: * Scaling ( performed according to the instruction ...
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Section 2 CPU Table 2.5 lists the data transfer instructions Table 2.5 Data Transfer Instructions Instruction Operation imm MOV #imm,Rn (disp MOV.W @(disp,PC),Rn extension (disp MOV.L @(disp,PC),Rn Rm MOV Rm,Rn Rm MOV.B Rm,@Rn Rm MOV.W Rm,@Rn Rm MOV.L Rm,@Rn (Rm) ...
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Instruction Operation Rm MOV.W Rm,@(R0,Rn) Rm MOV.L Rm,@(R0,Rn) (R0 + Rm) MOV.B @(R0,Rm),Rn extension (R0 + Rm) MOV.W @(R0,Rm),Rn extension (R0 + Rm) MOV.L @(R0,Rm),Rn R0,@(disp,GBR) R0 MOV.B R0,@(disp,GBR) R0 MOV.W R0,@(disp,GBR) R0 MOV.L @(disp,GBR),R0 (disp + GBR) MOV.B extension ...
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Section 2 CPU Table 2.6 lists the arithmetic instructions. Table 2.6 Arithmetic Instructions Instruction Operation ADD Rm, imm ADD #imm, ADDC Rm,Rn Carry ADDV Rm,Rn Overflow ...
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Instruction Operation Signed operation of DMULS.L Rm, MACL 32 Unsigned operation of DMULU.L Rm, MACL 32 Rn – else 0 A byte sign- EXTS.B Rm,Rn extended A ...
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Section 2 CPU Instruction Operation Rn–Rm SUB Rm,Rn Rn–Rm–T SUBC Rm,Rn Borrow Rn–Rm SUBV Rm,Rn Underflow Note: * The normal number of execution cycles is shown. The value in parentheses is the number of cycles required in case of contention ...
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Table 2.7 lists the logic operation instructions. Table 2.7 Logic Operation Instructions Instruction Operation Rn & Rm AND Rm,Rn R0 & imm AND #imm,R0 (R0 + GBR) & imm AND.B #imm,@(R0,GBR) (R0 + GBR) ~Rm NOT Rm, ...
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Section 2 CPU Table 2.8 lists the shift instructions. Table 2.8 Shift Instructions Instruction Operation T Rn ROTL Rn LSB Rn ROTR ROTCL ROTCR << Rm SHAD Rm,Rn Rn < ...
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Table 2.9 lists the branch instructions. Table 2.9 Branch Instructions Instruction Operation disp BF label nop (where label is disp + PC) Delayed branch BF/S label disp ...
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Section 2 CPU Table 2.10 lists the system control instructions. Table 2.10 System Control Instructions Instruction Operation 0 MACH, MACL CLRMAC 0 S CLRS 0 T CLRT Rm SR LDC Rm,SR Rm GBR LDC Rm,GBR Rm VBR LDC Rm,VBR Rm ...
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Instruction Operation (Rm) R4_BANK, LDC.L @Rm R4_BANK (Rm) R5_BANK, LDC.L @Rm R5_BANK (Rm) R6_BANK, LDC.L @Rm R6_BANK (Rm) R7_BANK, LDC.L @Rm R7_BANK Rm MACH LDS Rm,MACH Rm MACL ...
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Section 2 CPU Instruction Operation R4_BANK STC R4_BANK,Rn R5_BANK STC R5_BANK,Rn R6_BANK STC R6_BANK,Rn R7_BANK STC R7_BANK,Rn Rn–4 STC.L SR,@–Rn Rn–4 STC.L GBR,@–Rn Rn–4 STC.L VBR,@–Rn Rn–4 STC.L SSR,@–Rn Rn–4 STC.L SPC,@–Rn Rn–4 STC.L R0_BANK, @–Rn Rn–4 STC.L R1_BANK, @–Rn ...
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Notes: The table shows the minimum number of execution cycles. The actual number of instruction execution cycles will increase in cases such as the followings: a. When there is contention between an instruction fetch and data access b. When the ...
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Section 2 CPU 2.4.2 Instruction Code Map Table 2.11 shows the instruction code map. Table 2.11 Instruction Code Map Instruction Code Fx: 0000 MD: 00 MSB LSB 0000 Rn Fx 0000 0000 Rn Fx 0001 0000 Rn 00MD 0010 STC ...
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Instruction Code Fx: 0000 MD: 00 MSB LSB 0100 Rn Fx 0000 SHLL Rn 0100 Rn Fx 0001 SHLR Rn 0100 Rn Fx 0010 STS.L MACH,@-Rn 0100 Rn 00MD 0011 STC.L SR,@-Rn 0100 Rn 01MD 0011 STC.L SPC,@-Rn 0100 Rn ...
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Section 2 CPU Instruction Code Fx: 0000 MD: 00 MSB LSB 0110 Rn Rm 10MD SWAP.B Rm,Rn 0110 Rn Rm 11MD EXTU.B Rm,Rn 0111 Rn imm ADD #imm:8,Rn 1000 00MD Rn disp MOV.B R0,@(disp:4,Rn) 1000 01MD Rm disp MOV.B @(disp:4,Rm),R0 ...
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Processor States and Processor Modes 2.5.1 Processor States The SH7706 has five processor states: the reset state, exception-handling state, bus-released state, program execution state, and power-down state. Reset State: In this state the CPU is reset. The CPU enters ...
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Section 2 CPU From any state when RESETP = 0 Power-on reset Interrupt Bus-released state Bus Bus request request clearance Sleep mode RESETP=0 Note: * The hardware standby mode is entered when the CA pin goes low ...
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Section 3 Memory Management Unit (MMU) This LSI has an on-chip memory management unit (MMU) that implements address translation. This LSI's features a resident translation look-aside buffer (TLB) that caches information for user- created address translation tables located in external ...
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Section 3 Memory Management Unit (MMU) Although the functions of the MMU could also be implemented by software alone, the need for translation to be performed by software each time a process accesses physical memory would result in poor efficiency. ...
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This LSI's MMU Virtual Address Map: This LSI uses 32-bit virtual addresses to access a 4-Gbyte virtual address space that is divided into several areas. Address space mapping is shown in figure 3.2. In the privileged mode, the virtual ...
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Section 3 Memory Management Unit (MMU) H'00000000 2-Gbyte virtual space, cacheable (write-back/write-through) H'80000000 0.5-Gbyte fixed physical space, cacheable (write-back/write-through) H'A0000000 0.5-Gbyte fixed physical space, non-cacheable H'C0000000 0.5-Gbyte virtual space, cacheable (write-back/write-through) H'E0000000 0.5-Gbyte control space, non-cacheable H'FFFFFFFF Privileged mode Figure ...
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Physical Address Space: This LSI supports a 32-bit physical address space, but the upper 3 bits are actually ignored and treated as a shadow. See section 8, Bus State Controller (BSC), for details. Address Translation: When the MMU is enabled, ...
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Section 3 Memory Management Unit (MMU) Address Space Identifier (ASID): In multiple virtual memory mode, the address space identifier (ASID) is used to differentiate between processes running in parallel and sharing virtual address space. The ASID is 8 bits in ...
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Page Table Entry Register High (PTEH) The page table entry register high (PTEH) consists of a virtual page number (VPN) and ASID. The VPN is set the VPN of the virtual address at which the exception is generated in ...
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Section 3 Memory Management Unit (MMU) 3.2.3 The Translation Table Base Register (TTB) The translation table base register (TTB 32-bit register. TTB is used to store the base address of the current page table. The contents of this ...
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Initial Bit Bit Name Value All All All Section 3 Memory Management Unit (MMU) R/W Description ...
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Section 3 Memory Management Unit (MMU) 3.3 TLB Functions 3.3.1 Configuration of the TLB The TLB caches address translation table information located in the external memory. The address translation table stores the physical page number translated from the virtual page ...
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VPN Virtual address (1-kbyte page) 31 VPN Virtual address (4-kbyte page) (15) (2) (8) VPN (31–17) VPN (11, 10) ASID Legend VPN: Virtual page number. Top 22 bits of virtual address for a 1-kbyte page, or top 20 bits ...
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Section 3 Memory Management Unit (MMU) 3.3.2 TLB Indexing The TLB uses a 4-way set associative scheme, so entries must be selected by index. VPN bits and ASID bits in PTEH are used as ...
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Virtual address 31 17 Index 0 VPN(31–17) VPN(11, 10) 31 Address array 3.3.3 TLB Address Comparison The results of address comparison determine whether a specific virtual page number is registered in the TLB. The virtual page number of the virtual ...
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Section 3 Memory Management Unit (MMU) When single virtual memory is supported (MMUCR.SV (SR.MD 1), all process resources can be accessed. This means that ASIDs are not compared when single virtual memory is supported and privileged mode is engaged. The ...
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Page Management Information In addition to the SH and SZ bits, the page management information of TLB entries also includes D, C, and PR bits. The D bit of a TLB entry indicates whether the page is dirty (i.e., ...
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Section 3 Memory Management Unit (MMU) 3.4 MMU Functions 3.4.1 MMU Hardware Management There are two kinds of MMU hardware management as follows: 1. The MMU decodes the virtual address accessed by a process and performs address translation by controlling ...
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MMU Instruction (LDTLB) The load TLB instruction (LDTLB) is used to record TLB entries. When the IX bit in MMUCR is 0, the LDTLB instruction changes the TLB entry in the way specified by the RC bit in MMUCR ...
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Section 3 Memory Management Unit (MMU) 3.4.4 Avoiding Synonym Problems When a 1-kbyte page is recorded in a TLB entry, a synonym problem may arise number of virtual addresses are mapped onto a single physical address, the same ...
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When using a 4-kbyte page Virtual address VPN Physical address PPN When using a 1-kbyte page Virtual address 31 VPN Physical address 31 PPN Figure 3.9 Synonym Problem Section 3 Memory Management Unit (MMU) ...
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Section 3 Memory Management Unit (MMU) 3.5 MMU Exceptions There are four MMU exceptions: TLB miss, TLB protection violation, TLB invalid, and initial page write. 3.5.1 TLB Miss Exception A TLB miss results when the virtual address and the address ...
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Software (TLB Miss Handler) Operations: The software searches the page tables in external memory and allocates the required page table entry. Upon retrieving the required page table entry, software must execute the following operations: 1. Write the value of the ...
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Section 3 Memory Management Unit (MMU) Software (TLB Protection Violation Handler) Operations: Software resolves the TLB protection violation and issues the RTE (return from exception handler) instruction to terminate the handler and return to the instruction stream. Note that the ...
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Issue the RTE instruction to terminate the handler and return to the instruction stream. The RTE instruction should be issued after two LDTLB instructions. 3.5.4 Initial Page Write Exception An initial page write exception results in a write access ...
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Section 3 Memory Management Unit (MMU) Figure 3.10 shows the flowchart for MMU exceptions. No VPNs match? TLB miss exception PR check 00/01 W R/W? TLB protection violation exception No (noncacheable) Initial page write exception Memory access Figure 3.10 MMU ...
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Processing Flow in Event of MMU Exception (Same Processing Flow for CPU Address Error) Figure 3.11 shows the MMU exception signals in the instruction fetch mode. : Exception source stage Legend Instruction fetch ID = Instruction decode ...
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Section 3 Memory Management Unit (MMU) Figure 3.12 shows the MMU exception signals in the data access mode Exception source stage : Stage cancellation for instruction that has begun execution Legend Instruction fetch ...
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Configuration of the Memory-Mapped TLB In order for TLB operations to be managed by software, TLB contents can be read or written to in the privileged mode using the MOV instruction. The TLB is assigned to the P4 area ...
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Section 3 Memory Management Unit (MMU) Both reading and writing use the longword of the data array specified by the entry address and way number. The access size of the data array is fixed at longword. (1) TLB Address Array ...
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Usage Examples Invalidating Specific Entries: Specific TLB entries can be invalidated by writing 0 to the entry's V bit. R0 specifies the write data and R1 specifies the address. ; R0=H'1547 381C R1=H'F201 3000 ; MMUCR.IX=0 ; VPN(31–17)=B'000 1010 ...
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Section 3 Memory Management Unit (MMU) 3.7.2 Use of TLB An erroneous value is set in the RC bit in MMUCR when all of the following conditions are satisfied. 1. MMU is on (AT bit in MMUCR ...
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Section 4 Exception Processing 4.1 Exception Processing Function Exception processing is separate from normal program processing, and is performed by a routine separate from the normal program. In response to an exception processing request due to abnormal termination of the ...
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Section 4 Exception Processing 4.1.2 Exception Processing Vector Addresses The reset vector address is fixed at H'A0000000. The other three events are assigned offsets from the vector base address by software. Translation look-aside buffer (TLB) miss exceptions have an offset ...
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Exception Current Type Instruction Exception Event General Aborted TLB protection violation exception and retried (instruction access) events General illegal instruction exception Illegal slot instruction exception CPU Address error (data access) TLB miss (data access not in repeat loop) TLB invalid ...
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Section 4 Exception Processing All general exception events occur in a relative order in the execution sequence of an instruction (i.e. execution order), but are handled at priority level 2 in instruction-stream order (i.e. program order), where an exception detected ...
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All exceptions other than a reset are detected in the pipeline ID stage, and accepted on instruction boundaries. However, an exception is not accepted between a delayed branch instruction and the delay slot. A re-execution type exception detected in a ...
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Section 4 Exception Processing Exception Type General interrupt requests Note: Exception codes H'120, H'140, and H'3E0 are reserved. 4.1.5 Exception Request and BL Bit If a general exception event occurs when the BL bit the CPU's ...
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If the SPC and SSR have been saved in the external memory, set the BL bit then restore the SPC and SSR, and issue an RTE instruction. 4.2 Register Description There are four registers related to ...
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Section 4 Exception Processing 4.2.2 Interrupt Event Register (INTEVT) The interrupt event register (INTEVT) contains a 12-bit interrupt exception code or a code indicating the interrupt priority. Which is set when an interrupt occurs depends on the interrupt source (refer ...
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TRAPA Exception Register (TRA) The TRAPA exception register (TRA) contains 8-bit immediate data (imm) for the TRAPA instruction. TRA is set automatically by hardware when a TRAPA instruction is executed. TRA can also be modified by software. Bit Bit ...
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Section 4 Exception Processing 4.3.2 Interrupts An interrupt processing request is accepted on completion of the current instruction. The interrupt acceptance sequence consists of the following operations: 1. The contents of the PC and SR are saved in SPC and ...
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Individual Exception Operations This section describes the conditions for specific exception processing, and the processor operations. 4.4.1 Resets Power-On Reset Conditions: RESETP low Operations: EXPEVT set to H'000, VBR and SR initialized, branch to PC Initialization sets the VBR ...
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Section 4 Exception Processing Table 4.3 Types of Reset Conditions for Transition Type to Reset State RESETP = Low Power-on reset RESETM = Low Manual reset H-UDI reset H-UDI reset command input 4.4.2 General Exceptions TLB miss exception Conditions: Comparison ...
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Initial page write exception Conditions: A hit occurred to the TLB for a store access, but D writes to the page registered by the load.) Operations: The virtual address (32 bits) that caused the exception is set in TEA and ...
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Section 4 Exception Processing Operations: The virtual address (32 bits) that caused the exception is set in TEA. The PC and SR of the instruction that generated the exception are saved to the SPC and SSR, respectively. If the exception ...
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C. When a privileged instruction in a delay slot is decoded in user mode Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR with LDC/STC are not privileged instructions. Operations: The PC of the previous delay branch instruction ...
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Section 4 Exception Processing IRL Interrupts Conditions: The value of the interrupt mask bits lower than the IRL3 to IRL0 level and the BL bit The interrupt is accepted at an instruction boundary. ...
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Usage Note Return from exception processing Check the BL bit in SR with software. When the SPC and SSR have been saved to external memory, set the BL bit before restoring them. Issue an RTE ...
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Section 4 Exception Processing SR. SR. SR. SR.I3 to SR.I0 = H'F, SR. Other SR bits are undefined H'A0000000 Ensure that an exception is not generated at an RTE instruction ...
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Feature Instruction/data mixed, 16-byte cache 256 entries/way, 4-way set associative, 16-byte block Write-back/write-through selectable LRU replacing algorithm 1-stage write-back buffer A maximum of two ways lockable 5.1.1 Cache Structure The cache uses a 4-way set associative system ...
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Section 5 Cache Address Array: The V bit indicates whether the entry data is valid. When the V bit is 1, data is valid; when 0, data is not valid. The U bit indicates whether the entry has been written ...
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Register Description The cache includes the following registers. Refer to section 23, List of Registers, for more details of the addresses and access sizes. Cache control register (CCR) Cache control register 2 (CCR2) 5.2.1 Cache Control Register (CCR) The ...
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Section 5 Cache 5.2.2 Cache Control Register 2 (CCR2) Cache control register 2 (CCR2) enables or disables the cache locking mechanism. This register setting is valid only in cache locking mode. Cache locking mode is enabled when the cache locking ...
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Bit Bit Name Initial Value 1 W2LOAD 0 0 W2LOCK 0 Note: Do not set 1 into W2LOAD and W3LOAD at the same time. Whenever CCR2 bit 8 (W3LOCK) or bit 0 (W2LOCK) is high level the cache is locked. ...
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Section 5 Cache Table 5.3 Way to be Replaced when Cache Miss Occurs during Execution of Instruction Other than PREF Instruction CL bit W3LOAD W3LOCK ...
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Operation 5.3.1 Searching the Cache If the cache is enabled, whenever instructions or data in memory are accessed the cache will be searched to see if the desired instruction or data is in the cache. Figure 5.2 illustrates the ...
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Section 5 Cache Virtual address Entry selection 0 MMU 1 255 Physical address CMP0 CMP1 CMP2 CMP3 Legend: CMP0: Comparison circuit 0 CMP1: Comparison circuit 1 CMP2: Comparison circuit 2 CMP3: Comparison circuit 3 Figure 5.2 Cache ...
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Prefetch Operation Prefetch Hit: LRU is updated so that the way that has been hit to be the latest. Other contents of the cache are not updated. Instruction or data is not transferred to the CPU. Prefetch Miss: Instruction ...
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Section 5 Cache 5.3.6 Coherency of Cache and External Memory Use software to ensure coherency between the cache and the external memory. To allocate memory shared by this LSI and the external device to an address area to be cached, ...
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However, when 0 is written to the V bit, 0 must also be written to the U bit of that entry. Address Array Write (with associative operation): When writing while the ...
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Section 5 Cache (1) Address array access Address specification Read access 1111 0000 * Write access 1111 0000 * Data specification (both read and write accesses) 313029 Address tag (28–10) (2) ...
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Usage Examples 1. Invalidating Specific Entries Specific cache entries can be invalidated by writing 0 to the entry's U and V bit. When the A bit is 1, the address tag specified by the write data is compared to ...
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Section 5 Cache Rev. 5.00 May 29, 2006 page 112 of 698 REJ09B0146-0500 ...
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Section 6 Interrupt Controller (INTC) The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC has registers for setting the priority of each interrupt, and interrupt requests are handled according to ...
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Section 6 Interrupt Controller (INTC) Figure 6 block diagram of the INTC. IRQOUT NMI IRL3 to IRL0 4 IRQ0 to IRQ5 6 (Interrupt request) DMAC (Interrupt request) SCIF (Interrupt request) SCI (Interrupt request) ADC (Interrupt request) TMU (Interrupt ...
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Input/Output Pin Table 6.1 lists the INTC pin configuration. Table 6.1 Pin Configuration Name Nonmaskable interrupt input pin Interrupt input pins Interrupt request output pin 6.3 Interrupt Sources There are 4 types of interrupt sources: NMI, IRQ, IRL, and ...
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Section 6 Interrupt Controller (INTC possible to wake the chip up from the software standby state with an NMI interrupt (except when the MAI bit of the ICR1 register is set to 1). 6.3.2 IRQ Interrupt IRQ interrupts ...
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IRL Interrupts IRL interrupts are input by level at pins IRL3 to IRL0. The priority level is the higher of those indicated by pins IRL3 to IRL0. An IRL3 to IRL0 value of 0 (0000) indicates the highest-level interrupt ...
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Section 6 Interrupt Controller (INTC) A noise-cancellation feature is built in, and the IRL interrupt is not detected unless the levels sampled at every supporting module cycle remain unchanged for two consecutive cycles, so that no transient level on the ...
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Interrupt Exception Processing and Priority Tables 6.3 and 6.4 lists the codes for the interrupt event register (INTEVT and INTEVT2), and the order of interrupt priority. Each interrupt source is assigned unique code. The start address of the interrupt ...
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Section 6 Interrupt Controller (INTC) INTEVT Code Interrupt Source (INTEVT2 Code) H'200 to 3C0 * (H'980) ADC ADI TMU0 TUNI0 H'400 (H'400) TMU1 TUNI1 H'420 (H'420) TMU2 TUNI2 H'440 (H'440) TICPI2 H'460 (H'460) RTC ATI H'480 (H'480) PRI H'4A0 (H'4A0) ...
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Table 6.4 Interrupt Exception Handling Sources and Priority (IRL Mode) INTEVT Code Interrupt Source (INTEVT2 Code) NMI H'1C0 (H'1C0) H-UDI H'5E0 (H'5E0) IRL(3:0) = 0000 IRL H'200 (H'200) IRL(3:0) = 0001 H'220 (H'220) IRL(3:0) = 0010 H'240 (H'240) IRL(3:0) = ...
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Section 6 Interrupt Controller (INTC) INTEVT Code Interrupt Source (INTEVT2 Code) TMU0 TUNI0 H'400 (H'400) TMU1 TUNI1 H'420 (H'420) TMU2 TUNI2 H'440 (H'440) TICPI2 H'460 (H'460) RTC ATI H'480 (H'480) PRI H'4A0 (H'4A0) CUI H'4C0 (H'4C0) SCI ERI H'4E0 (H'4E0) ...
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Table 6.5 Interrupt Level and INTEVT Code Interrupt level INTEVT Code 15 H'200 14 H'220 13 H'240 12 H'260 11 H'280 10 H'2A0 9 H'2C0 8 H'2E0 7 H'300 6 H'320 5 H'340 4 H'360 3 H'380 2 H'3A0 1 ...
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Section 6 Interrupt Controller (INTC) 6.4.1 Interrupt Priority Registers (IPRA to IPRE) The interrupt priority level setting registers (IPRA to IPRE) are 16-bit read/write registers that set priority levels from for ...
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Interrupt Control Register 0 (ICR0) The interrupt control register 0 (ICR0 16-bit register that sets the input signal detection mode of the external interrupt input pin NMI and indicates the input signal level to the NMI pin. ...
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Section 6 Interrupt Controller (INTC) 6.4.3 Interrupt Control Register 1 (ICR1) The interrupt control register 1 (ICR1 16-bit register that specifies the detection mode to external interrupt input pins, IRQ0 to IRQ5 individually: rising edge, falling edge, or ...
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Bit Bit Name Initial Value 11 IRQ51S 0 10 IRQ50S 0 9 IRQ41S 0 8 IRQ40S 0 7 IRQ31S 0 6 IRQ30S 0 Section 6 Interrupt Controller (INTC) R/W Description R/W IRQ5 Sense Select R/W Select whether the interrupt signal ...
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Section 6 Interrupt Controller (INTC) Bit Bit Name Initial Value 5 IRQ21S 0 4 IRQ20S 0 3 IRQ11S 0 2 IRQ10S 0 1 IRQ01S 0 0 IRQ00S 0 Rev. 5.00 May 29, 2006 page 128 of 698 REJ09B0146-0500 R/W Description ...
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Interrupt Request Register 0 (IRR0) The interrupt request register 0 (IRR0 8-bit register that indicates interrupt requests from external input pins IRQ0 to IRQ5. To clear one of bits IRQ5R to IRQ0R to 0, first read the ...
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Section 6 Interrupt Controller (INTC) Bit Bit Name Initial Value R/W 2 IRQ2R 0 1 IRQ1R 0 0 IRQ0R 0 Rev. 5.00 May 29, 2006 page 130 of 698 REJ09B0146-0500 Description R/W IRQ2 Interrupt Request Indicates whether an interrupt request ...
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Interrupt Request Register 1 (IRR1) The interrupt request register 1 (IRR1 8-bit read-only register that indicates whether DMAC or IrDA interrupt requests are generated. Bit Bit Name Initial Value R — All 0 3 ...
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Section 6 Interrupt Controller (INTC) 6.4.6 Interrupt Request Register 2 (IRR2) The interrupt request register 2 (IRR2 8-bit read-only register that indicates whether A/D converter, or SCIF interrupt requests are generated. Bit Bit Name Initial Value R/W 7 ...
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Operation 6.5.1 Interrupt Sequence The sequence of interrupt operations is explained below. Figure 6 flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the ...
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Section 6 Interrupt Controller (INTC) source flag after it has been cleared, then wait for the interval shown in "Time for priority decision and SR mask bit comparison" in table 6.7 before clearing the BL bit or executing an RTE ...
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Multiple Interrupts When multiple interrupts are used, the structure of the interrupt service routine should be as follows. 1. Branch to a specific interrupt handler corresponding to a code set in INTEVT and INTEVT2. The code in INTEVT and ...
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Section 6 Interrupt Controller (INTC) Table 6.7 Interrupt Response Time Item NMI Time for priority 0.5 × Icyc decision and SR + 1.5 × Bcyc mask bit comparison Wait time until end × Icyc ...
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Item NMI Response Total (5 time Icyc + 1.5 Bcyc Minimum 7 case Maximum 10 case Icyc: Duration of one cycle of Bcyc: Duration of one cycle of B Pcyc: Duration of one cycle of Notes: ...
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Section 6 Interrupt Controller (INTC) 0.5 + 0.5 + 3.5 IRL Instruction (instruction replaced by interrupt exception processing) Overrun fetch First instruction of interrupt handler Legend: IF: Instruction fetch: Instruction is fetched from memory in which program is stored. ID: ...
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Section 7 User Break Controller The UBC provides functions that simplify program debugging. Using this function, a self-monitor debugger can be easily prepared, and a program can be debugged using this LSI alone, without using an in-circuit emulator. Instruction fetches, ...
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Section 7 User Break Controller Access IAB LAB Control LDB/IDB CPU state signals Legend: BBRA : Break bus cycle register A BARA : Break address register A BAMRA : Break address mask register A BASRA : Break ASID register A ...
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Register Description The UBC has the following registers. Refer to section 23, List of Registers, for more details of the addresses and access sizes. Break address register A (BARA) Break address mask register A (BAMRA) Break bus cycle register ...
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Section 7 User Break Controller 7.2.2 Break Address Mask Register A (BAMRA) BAMRA is a 32-bit read/write register. BAMRA specifies bits masked in the break address specified by BARA. Bit Bit Name Initial Value BAMA31 to All ...
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Bit Bit Name Initial Value — All 0 7 CDA1 0 6 CDA0 0 5 IDA1 0 4 IDA0 0 3 RWA1 0 2 RWA0 0 1 SZA1 0 0 SZA0 0 Legend: X: Don't care Section ...
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Section 7 User Break Controller 7.2.4 Break Address Register B (BARB) BARB is a 32-bit read/write register. BARB specifies the address used as a break condition in channel B. Bit Bit Name Initial Value BAB31 to All ...
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Break Data Mask Register B (BDMRB) BDMRB is a 32-bit read/write register. BDMRB specifies bits masked in the break data specified by BDRB. Bit Bit Name Initial Value R BDMB31 to All 0 BDMB0 Notes: n ...
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Section 7 User Break Controller Bit Bit Name Initial Value 5 IDB1 0 4 IDB0 0 3 RWB1 0 2 RWB0 0 1 SZB1 0 0 SZB0 0 Legend: X: Don't care Rev. 5.00 May 29, 2006 page 146 of ...
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Break Control Register (BRCR) BRCR sets the following conditions: 1. Channels A and B are used in two independent channels condition or under the sequential condition break is set before or after instruction execution break ...
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Section 7 User Break Controller Bit Bit Name Initial Value 15 SCMFCA 0 14 SCMFCB 0 13 SCMFDA 0 12 SCMFDB 0 Rev. 5.00 May 29, 2006 page 148 of 698 REJ09B0146-0500 R/W Description R/W CPU Condition Match Flag A ...
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Bit Bit Name Initial Value 11 PCTE 0 10 PCBA — All 0 7 DBEB 0 6 PCBB — All 0 Section 7 User Break Controller R/W Description R/W PC Trace Enable Enables PC ...
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Section 7 User Break Controller Bit Bit Name Initial Value 3 SEQ — All 0 0 ETBE 0 7.2.10 Execution Times Break Register (BETR) When the execution-times break condition of channel B is enabled, this register specifies ...