HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 143

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Initial page write exception
The PC and SR of the instruction that generated the exception are saved to the SPC and SSR,
respectively. H'080 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a
branch occurs in PC
TLB protection exception
The PC and SR of the instruction that generated the exception are saved to the SPC and SSR,
respectively. If the exception occurred during a read, H'0A0 is set in EXPEVT; if the exception
occurred during a write, H'0C0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1
and a branch occurs to PC = VBR + H'0100.
Address error
A. Instruction fetch from odd address (4n + 1, 4n + 3)
B. Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3)
C. Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2,
D. Virtual space accessed in user mode in the area H'80000000 to H'FFFFFFFF.
Conditions: A hit occurred to the TLB for a store access, but D
writes to the page registered by the load.)
Operations: The virtual address (32 bits) that caused the exception is set in TEA and the
corresponding virtual page number (22 bits) is set in PTEH (31 to 10). The ASID of PTEH
indicates the ASID at the time the exception occurred. The way that generated the
exception is set in the RC bit in MMUCR.
Conditions: When a hit access violates the TLB protection information (PR bits) shown
below:
Operations: The virtual address (32 bits) that caused the exception is set in TEA and the
corresponding virtual page number (22 bits) is set in PTEH (31 to 10). The ASID of PTEH
indicates the ASID at the time the exception occurred. The way that generated the
exception is set in the RC bits in MMUCR.
Conditions: When corresponded to the following items.
4n + 3)
PR
00
01
10
11
Privileged mode
Only read enabled
Read/write enabled
Only read enabled
Read/write enabled
VBR + H'0100.
User mode
No access
No access
Only read enabled
Read/write enabled
Rev. 5.00 May 29, 2006 page 93 of 698
Section 4 Exception Processing
0. (This occurs for initial
REJ09B0146-0500