HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 506

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 16 Serial Communication Interface with FIFO (SCIF)
Bit
4
3
Rev. 5.00 May 29, 2006 page 456 of 698
REJ09B0146-0500
Bit Name
BRK
FER
Initial
Value
0
0
R/W
R/(W) * Break Detection
R
Description
Indicates that a break signal is detected in received data.
0: No break signal is being received.
1: A break signal is received.
Note: When a break is detected, transfer of the received
Framing Error
Indicates a framing error in the data read from the
SCFRDR2.
0: No framing error occurred in the data read from
1: A framing error occurred in the data read from
SCFRDR2.
[Clearing conditions]
1. The chip is power-on reset or enters standby mode.
2. BRK is read as 1, then written to with 0.
[Setting conditions]
1. Data including a framing error is received.
2. A framing error with space 0 occurs in the subsequent
[Clearing conditions]
1. The chip is power-on reset or enters standby mode.
2. No framing error is present in the data read from
[Setting condition]
A framing error is present in the data read from
SCFRDR2
SCFRDR2.
received data.
SCFRDR2.
data (H'00) to SCFRDR2 stops after detection.
When the break ends and the receive signal
becomes mark 1, the transfer of the received data
resumes. The received data of a frame in which a
break signal is detected is transferred to SCFRDR2.
After this, however, no received data is transferred
until a break ends with the received signal being
mark 1 and the next data is received.