HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 115

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

3.3.4
In addition to the SH and SZ bits, the page management information of TLB entries also includes
D, C, and PR bits.
The D bit of a TLB entry indicates whether the page is dirty (i.e., has been written to). If the D bit
is 0, an attempt to write to the page results in an initial page write exception. For physical page
swapping between secondary memory and main memory, for example, pages are controlled so that
a dirty page is paged out of main memory only after that page is written back to secondary
memory. To record that there has been a write to a given page in the address translation table in
memory, an initial page write exception is used.
The C bit in the entry indicates whether the referenced page resides in a cacheable or non-
cacheable area of memory. The PR field specifies the access rights for the page in privileged and
user modes and is used to protect memory. Attempts at nonpermitted accesses result in TLB
protection violation exceptions.
Access states designated by the D, C, and PR bits are shown in table 3.1.
Table 3.1
D bit
C bit
PR bit
Page Management Information
0
1
0
1
00
01
10
11
Access States Designated by D, C, and PR Bits
Reading
Permitted
Permitted
Permitted
(no caching)
Permitted
(with caching)
Permitted
Permitted
Permitted
Permitted
Privileged Mode
Writing
Initial page write
exception
Permitted
Permitted
(no caching)
Permitted
(with caching)
TLB protection
violation exception
Permitted
TLB protection
violation exception
Permitted
Section 3 Memory Management Unit (MMU)
Rev. 5.00 May 29, 2006 page 65 of 698
Reading
Permitted
Permitted
Permitted
(no caching)
Permitted
(with caching)
TLB protection
violation exception
TLB protection
violation exception
Permitted
Permitted
User Mode
Writing
Initial page write
exception
Permitted
Permitted
(no caching)
Permitted
(with caching)
TLB protection
violation exception
TLB protection
violation exception
TLB protection
violation exception
Permitted
REJ09B0146-0500