HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 474

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 15 Smart Card Interface
15.3.1
The smart card mode register (SCSCMR) is an 8-bit read/write register that selects smart card
interface functions.
Rev. 5.00 May 29, 2006 page 424 of 698
REJ09B0146-0500
Bit
7 to 4
3
2
1
0
Bit Name
—
SDIR
SINV
—
SMIF
Smart Card Mode Register (SCSCMR)
Initial Value
—
0
0
—
0
R/W
R
R/W
R/W
R
R/W
Description
Reserved
An undefined value are read from these bits.
Smart Card Data Transfer Direction
Selects the serial/parallel conversion format.
0: Contents of SCTDR are transferred as LSB first,
1: Contents of SCTDR are transferred as MSB first,
Smart Card Data Inversion
Specifies whether to invert the logic level of the data.
This function is used in combination with bit 3 for
transmitting and receiving with an inverse
convention card. SINV does not affect the logic level
of the parity bit. See section 15.4.4, Register
Settings, for information on how parity is set.
0: Contents of SCTDR are transferred unchanged,
1: Contents of SCTDR are inverted before transfer,
Reserved
An undefined value is read from this bit.
Smart Card Interface Mode Select
Enables the smart card interface function.
0: Smart card interface function disabled
1: Smart card interface function enabled
receive data is stored in SCRDR as LSB first.
receive data is stored in SCRDR as MSB first.
receive data is stored in SCRDR unchanged.
receive data is inverted before storage in SCRDR.