HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 590

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 19 A/D Converter (ADC)
19.6.2
Multi mode should be selected when performing multi channel A/D conversions on one or more
channels. When the ADST bit in ADCSR is set to 1 by software or external trigger input, A/D
conversion starts on the first channel in the group (AN0 when CH2 = 0). When two or more
channels are selected, after conversion of the first channel ends, conversion of the second channel
(AN1) starts immediately. When A/D conversions end on the selected channels, the ADST bit is
cleared to 0. The conversion results are transferred for storage into the A/D data registers
corresponding to the channels.
When the mode or analog input channel selection must be changed during A/D conversion, to
prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After
making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the
first channel in the group. The ADST bit can be set at the same time as the mode or channel
selection is changed.
Rev. 5.00 May 29, 2006 page 540 of 698
REJ09B0146-0500
Channel 0 (AN0)
Channel 1 (AN1)
Channel 2 (AN2)
Channel 3 (AN3)
Figure 19.5 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
operating
operating
operating
operating
ADDRA
ADDRB
ADDRC
ADDRD
Multi Mode (MULTI = 1, SCN = 0)
ADST
ADIE
ADF
Note: * Downward arrows ( ) indicate instruction execution.
A/D conversion starts
Waiting
Waiting
Waiting
Waiting
A/D conversion 1
Set *
Set *
A/D conversion result 2
A/D conversion result 1
Waiting
Clear *
Read result
Set *
A/D conversion result 2
Clear
Read result
Waiting