HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 150

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 5 Cache
Address Array: The V bit indicates whether the entry data is valid. When the V bit is 1, data is
valid; when 0, data is not valid. The U bit indicates whether the entry has been written to in write-
back mode. When the U bit is 1, the entry has been written to; when 0, it has not. The address tag
holds the physical address used in the external memory access. It is composed of 22 bits (address
bits 31 to 10) used for comparison during cache searches.
In the SH7706, the top three of 32 physical address bits are used as shadow bits (see section 8, Bus
State Controller (BSC)), and therefore in a normal replace operation the top three bits of the tag
address are cleared to 0.
The V and U bits are initialized to 0 by a power-on reset, but are not initialized by a manual reset.
The tag address is not initialized by either a power-on or manual reset.
Data Array: Holds a 16-byte instruction or data. Entries are registered in the cache in line units
(16 bytes). The data array is not initialized by a power-on or manual reset.
LRU: With the 4-way set associative system, up to four instructions or data with the same entry
address (address bits 11 to 4) can be registered in the cache. When an entry is registered, the LRU
bits show which of the four ways it is recorded in. There are six LRU bits, controlled by hardware.
A least recently used (LRU) algorithm, which selects the way that has been used least recently, is
used to select the way.
The LRU bits also indicate the way to be replaced when a cache miss occurs. Table 5.1 shows the
relationship between the LRU bits and the way to be replaced when cache locking mechanism is
disabled. (For details on the case when cache locking mechanism is enabled, see section 5.2.2,
Cache Control Register 2 (CCR2)). If a bit pattern other than those listed in table 5.1 is set in the
LRU bits by software, the cache will not function correctly. When modifying the LRU bits by
software, set one of the patterns listed in table 5.1.
The LRU bits are initialized to B'000000 by a power on reset, but are not initialized by a manual
reset.
Table 5.1
Rev. 5.00 May 29, 2006 page 100 of 698
REJ09B0146-0500
LRU (5 to 0)
000000, 000100, 010100, 100000, 110000, 110100
000001, 000011, 001011, 100001, 101001, 101011
000110, 000111, 001111, 010110, 011110, 011111
111000, 111001, 111011, 111100, 111110, 111111
LRU and Way Replacement
Way to be Replaced (when cache
locking mechanism is disabled)
3
2
1
0