HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 144

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 4 Exception Processing
Rev. 5.00 May 29, 2006 page 94 of 698
REJ09B0146-0500
Unconditional trap
General illegal instruction exception
A. When undefined code not in a delay slot is decoded
B. When a privileged instruction not in a delay slot is decoded in user mode
Illegal slot instruction exception
A. When undefined code in a delay slot is decoded
B. When an instruction that rewrites the PC in a delay slot is decoded
Operations: The virtual address (32 bits) that caused the exception is set in TEA. The PC
and SR of the instruction that generated the exception are saved to the SPC and SSR,
respectively. If the exception occurred during a read, H'0E0 is set in EXPEVT; if the
exception occurred during a write, H'100 is set in EXPEVT. The BL, MD, and RB bits in
SR are set to 1 and a branch occurs to PC
Processing Flow in Event of MMU Exception (Same Processing Flow for CPU Address
Error).
Conditions: TRAPA instruction executed
Operations: The exception is a processing-completion type, so the PC of the instruction
after the TRAPA instruction is saved to the SPC. SR from the time when the TRAPA
instruction was executing is saved to SSR. The 8-bit immediate value in the TRAPA
instruction is quadrupled and set in TRA (9 to 0). H'160 is set in EXPEVT. The BL, MD,
and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100.
Conditions: When corresponded to the following items.
Delay branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S
Undefined instruction: H'Fxxx.(In the case of SR.CL = 1, the value should be
B'111111xxxxxxxxxx.)
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR
with LDC/STC are not privileged instructions.
Operations: The PC and SR of the instruction that generated the exception are saved to the
SPC and SSR, respectively. H'180 is set in EXPEVT. The BL, MD, and RB bits in SR are
set to 1 and a branch occurs to PC = VBR + H'0100. When an undefined instruction other
than H'Fxxx is decoded, operation cannot be guaranteed.
Conditions: When corresponded to the following items.
Delay branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S
Undefined instruction: H'Fxxx. (In the case of SR.CL = 1, the value should be
B'111111xxxxxxxxxx.)
Instructions that rewrite the PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF,
BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR
VBR + H'0100. Refer to section 3.5.5,