HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 265

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Table 8.18 Example of Correspondence between this LSI and Synchronous DRAM
Burst Read
Figure 8.13 shows the timing chart for a burst read. In the example below, it is assumed that four
2M
length is 1. Following the Tr cycle in which ACTV command output is performed, a READ
command is issued in the Tc1, Tc2, and Tc3 cycles, and a READA command in the Tc4 cycle, and
the read data is accepted on the rising edge of the external command clock (CKIO) from cycle Td1
to cycle Td4. The Tpc cycle is used to wait for completion of auto-precharge based on the
READA command inside the synchronous DRAM; no new access command can be issued to the
same bank during this cycle, but access to synchronous DRAM for another area is possible. In the
this LSI, the number of Tpc cycles is determined by the TPC bit specification in MCR, and
commands cannot be issued for the same synchronous DRAM during this interval.
8-bit synchronous DRAMs are connected and a 32-bit data width is used, and the burst
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Pin of this LSI
Address Pins (AMX (3 to 0) = 0100 (32-Bit Bus Width))
RAS Cycle
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
CAS Cycle
A23
A22
A13
A11
A10
L/H
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
A13(BA1)
A12(BA0)
Not used
Not used
Rev. 5.00 May 29, 2006 page 215 of 698
Synchronous DRAM Address Pin
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Section 8 Bus State Controller (BSC)
BANK select address
Address
Address/precharge setting
Address
Function
REJ09B0146-0500