HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 449

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Receiving Serial Data (Asynchronous Mode): Figure 14.10 shows a sample flowchart for
receiving serial data. Serial data reception should be carried out in the following procedure after
setting the SCI in a reception-enabled state.
No
No
and clear RDRF bit in SCSSR to 0
Clear the RE bit in SCSCR to 0
Read reception data of SCRDR
Read the RDRF bit in SCSSR
Read ORER, PER, and FER
Figure 14.10 Sample Flowchart for Receiving Serial Data
All data received?
Start reception
End reception
or ORER = 1?
bits in SCSSR
RDRF = 1?
PER = 1,
FER = 1,
No
Yes
Yes
Yes
Error processing
Section 14 Serial Communication Interface (SCI)
Rev. 5.00 May 29, 2006 page 399 of 698
1.
2.
3.
Receive error processing and break
detection: If a receive error occurs,
read the ORER, PER and FER bits
of the SCSSR to identify the error.
After executing the necessary error
processing, clear ORER, PER and
FER all to 0. Receiving cannot
resume if ORER, PER or FER remain
set to 1. When a framing error occurs,
the RxD0 pin can be read to detect the
break state.
SCI status check and receive-data read:
Read the SCSSR, check that RDRF is
set to 1, then read receive data from the
SCRDR and clear RDRF to 0. The RXI
interrupt can also be used to determine
if the RDRF bit has changed from 0 to 1.
To continue receiving serial data: Clear
RDRF to 0 before the stop bit of the
current frame is received.
REJ09B0146-0500