HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 165

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

6.2
Table 6.1 lists the INTC pin configuration.
Table 6.1
6.3
There are 4 types of interrupt sources: NMI, IRQ, IRL, and on-chip peripheral modules. The
priority of each interrupt is indicated by a priority level value (16 to 0), with level 16 as the
highest and level 1 as the lowest. When level 0 is set, the interrupt is masked and interrupt
requests are ignored.
6.3.1
The NMI interrupt has the highest priority level of 16. When the BLMSK bit of the interrupt
control register (ICR1) is 1 or the BL bit of the status register (SR) is 0, NMI interrupts are
accepted when the MAI bit of the ICR1 register is 0. NMI interrupts are edge-detected. In sleep or
software standby mode, the interrupt is accepted regardless of the BL. The NMI edge select bit
(NMIE) in the interrupt control register 0 (ICR0) is used to select either the rising or falling edge.
When the NMIE bit of the ICR0 register is changed, the NMI interrupt is not detected for 20
cycles after changing the ICR0. NMIE to avoid a false detection of the NMI interrupt. NMI
interrupt exception processing does not affect the interrupt mask level bits (I3 to I0) in the status
register (SR).
When the BL bit is 1 and the BLMSK bit of the ICR1 register is set to 1, only NMI interrupts are
accepted and the SPC register and SSR register are updated by the NMI interrupt handler, making
it impossible to return to the original processing from exception processing initiated prior to the
NMI. Use should therefore be restricted to cases where return is not necessary.
Name
Nonmaskable interrupt input pin
Interrupt input pins
Interrupt request output pin
Interrupt Sources
NMI Interrupts
Input/Output Pin
Pin Configuration
Abbreviation
NMI
IRQ5 to IRQ0
IRL3 to IRL0
IRQOUT
I/O
I
I
O
Rev. 5.00 May 29, 2006 page 115 of 698
Description
Nonmaskable interrupt request signal
input
Interrupt request signal input
(Maskable by interrupt mask bits in
SR)
Output of signal that notifies external
devices that an interrupt source or
memory refresh has occurred
Section 6 Interrupt Controller (INTC)
REJ09B0146-0500