HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 298

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 8 Bus State Controller (BSC)
8.5.8
When a bus release request (BREQ) is received from an external device, buses are released after
the bus cycle being executed is completed and a bus grant signal (BACK) is output The bus is not
released during burst transfers for cache fills or a write back and TAS instruction execution
between the read cycle and write cycle. Bus arbitration is not executed in multiple bus cycles that
are generated when the data bus width is shorter than the access size; i.e. in the bus cycles when
longword access is executed for the 8-bit memory. At the negation of BREQ, BACK is negated
and bus use is restarted See Appendix B, Pin Functions, for the pin state when the bus is released.
This LSI sometimes needs to retrieve a bus it has released. For example, when memory generates
a refresh request or an interrupt request internally, this LSI must perform the appropriate
processing. This LSI has a bus request signal (IRQOUT) for this purpose. When it must retrieve
the bus, it asserts the IRQOUT signal. Devices asserting an external bus release request receive the
assertion of the IRQOUT signal and negate the BREQ signal to release the bus. This LSI retrieves
the bus and carries out the processing.
Rev. 5.00 May 29, 2006 page 248 of 698
REJ09B0146-0500
CKIO
A25 to A0
CSm
CSn
BS
RD/WR
RD
D31 to D0
Bus Arbitration
Area m inter-access wait specification
T1
Area m read
Figure 8.39 Waits between Access Cycles
T2
Twait
Area n space read
T1
T2
Area n inter-access wait specification
Twait
Area n space write
T1
T2