HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 452

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 14 Serial Communication Interface (SCI)
Figure 14.11 shows an example of SCI receive operation in the asynchronous mode.
14.4.2
The multiprocessor communication function enables several processors to share a single serial
communication line. The processors communicate in the asynchronous mode using a format with
an additional multiprocessor bit (multiprocessor format).
In multiprocessor communication, each receiving processor is addressed by a unique ID. A serial
communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a
data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending
cycles. The transmitting processor starts by sending the ID of the receiving processor with which it
wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor
sends transmit data with the multiprocessor bit cleared to 0.
Receiving processors skip incoming data until they receive data with the multiprocessor bit set to
1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the
data with their IDs. The receiving processor with a matching ID continues to receive further
incoming data. Processors with IDs not matching the received data skip further incoming data
until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and
receive data in this way.
Rev. 5.00 May 29, 2006 page 402 of 698
REJ09B0146-0500
Example: 8-bit data with parity and one stop bit
Serial
data
RDRF
FER
Multiprocessor Communication
1
Start
bit
0
D 0
D 1
1 frame
Data
Figure 14.11 SCI Receive Operation
D 7
RXI interrupt request
generated
Parity
bit
0/1
Stop
bit
1
Start
0
bit
Reads data with
the RXI interrupt
processing routine
and clears RDRF
bit to 0
D 0
D 1
Data
D 7
Parity
bit
0/1
ERI interrupt
request generated
by framing error
Stop
bit
1
(marking)
1
Idling