HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 602

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 20 D/A Converter (DAC)
20.4
The D/A converter has two built-in D/A conversion circuits that can perform conversion
independently.
D/A conversion is performed constantly while enabled in DACR. If the DADR0 or DADR1 value
is modified, conversion of the new data begins immediately. The conversion results are output
when bits DAOE0 and DAOE1 are set to 1.
An example of D/A conversion on channel 0 is given next. Timing is indicated in figure 20.2.
1. Data to be converted is written in DADR0.
2. Bit DAOE0 is set to 1 in DACR. D/A conversion starts and DA0 becomes an output pin. The
3. If the DADR0 value is modified, conversion starts immediately, and the result is output after
4. When the DAOE0 bit is cleared to 0, DA0 becomes an input pin.
Rev. 5.00 May 29, 2006 page 552 of 698
REJ09B0146-0500
converted result is output after the conversion time. The output value is (DADR0 contents/256)
the DAOE0 bit is cleared to 0.
the conversion time.
Address bus
DADR0
DAOE0
DA0
Legend:
t
DCONV
AVcc. Output of this conversion result continues until the value in DADR0 is modified or
: D/A conversion time
Operation
write cycle
DADR0
High-impedance state
Figure 20.2 Example of D/A Converter Operation
write cycle
DACR
Conversion data 1
t
DCONV
Conversion
result 1
write cycle
DADR0
t
DCONV
Conversion data 2
Conversion
result 2
write cycle
DACR