HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 141

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

4.4
This section describes the conditions for specific exception processing, and the processor
operations.
4.4.1
Power-On Reset
Manual Reset
H-UDI Reset
Conditions: RESETP low
Operations: EXPEVT set to H'000, VBR and SR initialized, branch to PC
Initialization sets the VBR register to H'0000000. In SR, the MD, RB and BL bits are set to
1 and the interrupt mask bits (I3 to I0) are set to B'1111. The CPU and on-chip supporting
modules are initialized. For details, refer to section 23, List of Registers. A power-on reset
must always be performed when powering on.
A high level is output from the STATUS0 and STATUS1 pins.
Conditions: RESETM low
Operations: EXPEVT set to H'020, VBR and SR initialized, branch to PC
Initialization sets the VBR register to H'0000000. In SR, the MD, RB, and BL bits are set
to 1 and the interrupt mask bits (I3 to I0) are set to B'1111. The CPU and on-chip
supporting modules are initialized. For details, refer to section 23, List of Registers.
A high level is output from the STATUS0 and STATUS1 pins.
Conditions: H-UDI reset command input (see section 21, User Debugging Interface (H-
UDI))
Operations: EXPEVT set to H'000, VBR and SR initialized, branch to PC
Initialization sets the VBR register to H'0000000. In SR, the MD, RB and BL bits are set to
1 and the interrupt mask bits (I3 to I0) are set to B'1111. The CPU and on-chip supporting
modules are initialized. For details, refer to section 23, List of Registers.
Resets
Individual Exception Operations
Rev. 5.00 May 29, 2006 page 91 of 698
Section 4 Exception Processing
REJ09B0146-0500
H'A0000000.
H'A0000000.
H'A0000000.