HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 127

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

3.6
In order for TLB operations to be managed by software, TLB contents can be read or written to in
the privileged mode using the MOV instruction. The TLB is assigned to the P4 area in the virtual
address space. The TLB address array (VPN, V bit, and ASID) is assigned to H'F2000000 to
H'F2FFFFFF, and the data array (PPN, PR, SZ, C, D, and SH bits) to H'F3000000 to
H'F3FFFFFF. The V bit in the address array can also be accessed from the data array. Only
longword access is possible for both the address array and the data array.
3.6.1
The address array is assigned to H'F2000000 to H'F2FFFFFF. To access an address array, the
32-bit address field (for read/write operations) and 32-bit data field (for write operations) must be
specified. The address field specifies information for selecting the entry to be accessed; the data
field specifies the VPN, V bit and ASID to be written to the address array (figure 3.13 (1)).
In the address field, specify the entry address for selecting the entry (bits 16 to 12), W for selecting
the way (bits 9, 8: 00 is way 0, 01 is way 1, 10 is way 2, 11 is way 3) and H'F2 to indicate address
array access (bits 31 to 24). The IX bit in MMUCR indicates whether an EX-OR is taken of the
entry address and ASID.
When writing, the write is performed to the entry selected with the index address and way.
When reading, the VPN, V bit, and ASID of the entry selected with the index address and way in
the format of the data field in figure 3.13 without comparing addresses. 0 is written to data field
bits 16 to 12.
To invalidate a specific entry, specify the entry and way, and write 0 to the corresponding V bit.
3.6.2
The data array is assigned to H'F3000000 to H'F3FFFFFF. To access a data array, the 32-bit
address field (for read/write operations), and 32-bit data field (for write operations) must be
specified. These are specified in the general register. The address section specifies information for
selecting the entry to be accessed; the data section specifies the longword data to be written to the
data array (figure 3.13 (2)).
In the address section, specify the entry address for selecting the entry (bits 16 to 12), W for
selecting the way (bits 9, 8: 00 is way 0, 01 is way 1, 10 is way 2, 11 is way 3), and H'F3 to
indicate data array access (bits 31 to 24). The IX bit in MMUCR indicates whether an EX-OR is
taken of the entry address and ASID.
Address Array
Data Array
Configuration of the Memory-Mapped TLB
Section 3 Memory Management Unit (MMU)
Rev. 5.00 May 29, 2006 page 77 of 698
REJ09B0146-0500