HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 360

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 10 Clock Pulse Generator (CPG)
10.4
The CPG includes the following register. Refer to section 23, List of Registers, for more details of
the addresses and access sizes.
10.4.1
The frequency control register (FRQCR) is a 16-bit read/write register used to specify, the
frequency multiplication ratio of PLL circuit 1, and the frequency division ratio of the CPU clock
and the peripheral clock. Only word access can be used on the FRQCR register.
The FRQCR register is initialized to H'0102 at a power-on reset by the RESETP pin and retains its
previous value at a manual reset or in standby mode.
Rev. 5.00 May 29, 2006 page 310 of 698
REJ09B0146-0500
Bit
15
5
4
and
control register. The on/off state of PLL circuit 2 and the multiplication ratio are determined by
the mode.
Frequency control register (FRQCR)
1,
1/4 can be selected as the division ratios of dividers 1 and 2. Set the rate in the frequency
Register Description
Frequency Control Register (FRQCR)
2,
Bit Name
STC2
STC1
STC0
3, or
4 can be used as the multiplication ratio of PLL circuit 1.
Initial Value
0
0
0
R/W
R/W
R/W
R/W
Description
Frequency Multiplication Ratio
These bits specify the frequency multiplication ratio
of PLL circuit 1.
000:
001:
100:
010:
Other than the above: Reserved (Setting prohibited)
Note: Do not set the output frequency of PLL circuit
1
2
3
4
1 higher than 133 MHz.
1,
1/2,
3,