HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 29

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

8.5
Section 9 Direct Memory Access Controller (DMAC)
9.1
9.2
9.3
9.4
9.5
9.6
8.4.7
8.4.8
8.4.9
8.4.10 Refresh Time Constant Register (RTCOR) ......................................................... 196
8.4.11 Refresh Count Register (RFCR) .......................................................................... 197
Operation .......................................................................................................................... 197
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.5.7
8.5.8
8.5.9
Feature .............................................................................................................................. 251
Input/Output Pin................................................................................................................ 254
Register Description.......................................................................................................... 254
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
Operation .......................................................................................................................... 265
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
9.4.7
Compare Match Timer (CMT).......................................................................................... 292
9.5.1
9.5.2
9.5.3
Examples of Use ............................................................................................................... 298
9.6.1
Synchronous DRAM Mode Register (SDMR) .................................................... 193
Refresh Timer Control/Status Register (RTCSR) ................................................ 193
Refresh Timer Counter (RTCNT)........................................................................ 196
Endian/Access Size and Data Alignment............................................................. 197
Description of Areas ............................................................................................ 202
Basic Interface ..................................................................................................... 205
Synchronous DRAM Interface............................................................................. 211
Burst ROM Interface............................................................................................ 234
PCMCIA Interface ............................................................................................... 236
Waits between Access Cycles.............................................................................. 247
Bus Arbitration .................................................................................................... 248
Bus Pull-Up.......................................................................................................... 249
DMA Source Address Registers 0 to 3 (SAR_0 to SAR_3) ................................ 255
DMA Destination Address Registers 0 to 3 (DAR_0 to DAR_3)........................ 255
DMA Transfer Count Registers 0 to 3 (DMATCR_0 to DMATCR_3)............... 256
DMA Channel Control Registers 0 to 3 (CHCR_0 to CHCR_3)......................... 256
DMA Operation Register (DMAOR)................................................................... 263
DMA Transfer Flow ............................................................................................ 265
DMA Transfer Requests ...................................................................................... 267
Channel Priority ................................................................................................... 269
DMA Transfer Types........................................................................................... 272
Number of Bus Cycle States and DREQ Pin Sampling Timing .......................... 284
Source Address Reload Function ......................................................................... 288
DMA Transfer Ending Conditions....................................................................... 290
Feature ................................................................................................................. 292
Register Description............................................................................................. 293
Operation ............................................................................................................. 295
Example of DMA Transfer between A/D Converter and External Memory
(Address Reload on) ............................................................................................ 298
Rev. 5.00 May 29, 2006 page xxvii of xlviii
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